利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.014 秒)

    Over-voltage protection circuit
    1.
    发明授权
    Over-voltage protection circuit 有权
    过电压保护电路

    公开(公告)号：US09407084B2

    公开(公告)日：2016-08-02

    申请号：US14553989

    申请日：2014-11-25

    申请人： Mayank Jain ,  Sanjoy K. Dey

    发明人： Mayank Jain ,  Sanjoy K. Dey

    IPC分类号： H02H3/20

    CPC分类号： H02H3/20 ,  H02H9/046

    摘要： An over-voltage protection circuit suitable for use at a front-end of an on-chip analog module such as an analog-to-digital converter (ADC) includes an input potential divider that can be disconnected from the module when the module is idle (or working on any other input such as the ADC sampling another channel causing the current channel to be idle) while still providing protection for front-end devices. A first NMOS transistor pair connects or disconnects the potential divider to or from ground in response to a control signal, and a second transistor pair including a NMOS transistor and a PMOS transistor ensures that the output does not rise above the supply voltage.

    摘要翻译： 适用于诸如模数转换器（ADC）的片上模拟模块前端的过电压保护电路包括一个输入电位分压器，当模块空闲时可以与模块断开连接 （或在任何其他输入上工作，例如ADC对另一个通道进行采样，导致当前通道空闲），同时仍然为前端设备提供保护。 第一NMOS晶体管对响应于控制信号而将分压器连接或断开接地，并且包括NMOS晶体管和PMOS晶体管的第二晶体管对确保输出不升高到电源电压以上。

    OVER-VOLTAGE PROTECTION CIRCUIT
    2.
    发明申请
    OVER-VOLTAGE PROTECTION CIRCUIT 有权
    过电压保护电路

    公开(公告)号：US20160149391A1

    公开(公告)日：2016-05-26

    申请号：US14553989

    申请日：2014-11-25

    申请人： Mayank Jain ,  Sanjoy K. Dey

    发明人： Mayank Jain ,  Sanjoy K. Dey

    IPC分类号： H02H3/20

    CPC分类号： H02H3/20 ,  H02H9/046

    摘要： An over-voltage protection circuit suitable for use at a front-end of an on-chip analog module such as an analog-to-digital converter (ADC) includes an input potential divider that can be disconnected from the module when the module is idle (or working on any other input such as the ADC sampling another channel causing the current channel to be idle) while still providing protection for front-end devices. A first NMOS transistor pair connects or disconnects the potential divider to or from ground in response to a control signal, and a second transistor pair including a NMOS transistor and a PMOS transistor ensures that the output does not rise above the supply voltage.

    摘要翻译： 适用于诸如模数转换器（ADC）的片上模拟模块前端的过电压保护电路包括一个输入电位分压器，当模块空闲时可以与模块断开连接 （或在任何其他输入上工作，例如ADC对另一个通道进行采样，导致当前通道空闲），同时仍然为前端设备提供保护。 第一NMOS晶体管对响应于控制信号而将分压器连接或断开接地，并且包括NMOS晶体管和PMOS晶体管的第二晶体管对确保输出不升高到电源电压以上。

    Input control circuit for analog device
    3.
    发明授权
    Input control circuit for analog device 有权
    模拟设备输入控制电路

    公开(公告)号：US09325312B1

    公开(公告)日：2016-04-26

    申请号：US14568093

    申请日：2014-12-11

    申请人： Mayank Jain ,  Sanjoy K. Dey

    发明人： Mayank Jain ,  Sanjoy K. Dey

    IPC分类号： H03K17/687

    CPC分类号： H03K17/687 ,  H03K17/102

    摘要： An input control circuit that can be used to drive analog switches of analog modules such as an analog-to-digital converter (ADC) enables a sampling switch to receive a higher input voltage than the voltage rating of the devices comprising the sampling switch without risk of damage and without the need for a resistor divider network. The input control circuit and switch both receive an input voltage to be processed and the input control circuit generates a control signal for the switch that is derived from a pre-charged capacitor. The control circuit permits the design and manufacture of high voltage analog modules using low voltage devices, which can save on mask costs without any performance trade-offs.

    摘要翻译： 可用于驱动诸如模数转换器（ADC）的模拟模块的模拟开关的输入控制电路使采样开关能够接收比包含采样开关的器件的额定电压更高的输入电压，而不会有风险 的损坏，无需电阻分压网络。 输入控制电路和开关均接收要处理的输入电压，并且输入控制电路产生用于从预充电电容器导出的开关的控制信号。 控制电路允许使用低电压设备设计和制造高压模拟模块，这可以节省面罩成本，而无需任何性能折衷。

    Single capacitor, low leakage charge pump
    4.
    发明授权
    Single capacitor, low leakage charge pump 有权
    单电容器，低泄漏电荷泵

    公开(公告)号：US09300283B1

    公开(公告)日：2016-03-29

    申请号：US14624587

    申请日：2015-02-18

    申请人： Mayank Jain ,  Sanjoy K. Dey

    发明人： Mayank Jain ,  Sanjoy K. Dey

    IPC分类号： G05F1/10 ,  H03K5/134 ,  H02M3/07 ,  H03K5/00

    CPC分类号： H03K5/134 ,  H02M3/07 ,  H03K2005/00293

    摘要： A charge pump circuit includes a delay circuit, a transistor, and a capacitor. The charge pump receives an input signal and outputs an output signal. The delay circuit receives a first signal based on the input signal and outputs a first delayed signal. The transistor includes a gate, a first channel node, and a second channel node. The first channel node receives the first signal. The second channel node is connected to the output and to a first plate of the capacitor. A second plate of the capacitor receives a second signal based on the first delayed signal. The charge pump circuit is adapted to operate such that the voltage range of the output signal is greater than the voltage range of the input signal.

    摘要翻译： 电荷泵电路包括延迟电路，晶体管和电容器。 电荷泵接收输入信号并输出​​输出信号。 延迟电路基于输入信号接收第一信号并输出​​第一延迟信号。 晶体管包括栅极，第一沟道节点和第二沟道节点。 第一信道节点接收第一信号。 第二通道节点连接到电容器的输出端和第一板上。 电容器的第二板基于第一延迟信号接收第二信号。 电荷泵电路适于操作，使得输出信号的电压范围大于输入信号的电压范围。

    Successive approximation analog-to-digital converter with linearity error correction
    5.
    发明授权
    Successive approximation analog-to-digital converter with linearity error correction 有权
    具有线性误差校正的逐次逼近模数转换器

    公开(公告)号：US09071265B1

    公开(公告)日：2015-06-30

    申请号：US14457124

    申请日：2014-08-12

    申请人： Sanjoy K. Dey ,  Vikram Varma

    发明人： Sanjoy K. Dey ,  Vikram Varma

    IPC分类号： H03M1/10 ,  H03M1/14 ,  H03M1/12 ,  H03M1/80 ,  H03M1/06 ,  H03M1/00 ,  H03M7/16

    CPC分类号： H03M1/0695 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/12 ,  H03M1/468 ,  H03M1/804 ,  H03M7/165

    摘要： A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.

    摘要翻译： SAR ADC包括电容，比较器和SAR逻辑电路。 电容器包括第一组电容器和误差检测电容器。 第一组电容器产生第一组电压信号，该电压信号在第一组比较周期期间由比较器与共模电压信号（VCM）进行比较。 比较器产生第一组控制信号，由SAR逻辑电路用来连续近似第一组电压信号并产生第一组位。 误差检测电容器生成与比较器的共模电压信号VCM进行比较以产生检错控制信号的检错信号。 SAR逻辑电路基于错误检测控制信号的逻辑状态来补偿第一组位中的错误。

    Digital calibration of programmable gain amplifiers
    6.
    发明授权
    Digital calibration of programmable gain amplifiers 有权
    可编程增益放大器的数字校准

    公开(公告)号：US09112465B2

    公开(公告)日：2015-08-18

    申请号：US14067994

    申请日：2013-10-31

    申请人： Sanjoy K. Dey ,  Mayank Jain

    发明人： Sanjoy K. Dey ,  Mayank Jain

    IPC分类号： H03G1/00 ,  H03F1/02 ,  H03G3/00 ,  H03F3/45

    CPC分类号： H03G1/0088 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/321 ,  H03F2203/45048 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45536 ,  H03F2203/45594 ,  H03F2203/45616 ,  H03G3/001

    摘要： A programmable gain amplifier (PGA) includes an op amp, an input circuit, a feedback circuit, and a calibration circuit. The input circuit is connected between a PGA input node and an op-amp input node and selectively applies the analog input signal to the op-amp input node. The feedback circuit is connected between an op-amp output node and the op-amp input node and applies the amplified analog output signal as a feedback signal to the op-amp input node. The calibration circuit is connected between a calibration reference node and the op-amp input node and selectively connects the calibration reference node directly to the op-amp input node without traversing any of the input circuit. The PGA may be implemented as a single-ended or differential amplifier. The PGA avoids reduced linearity resulting from series combinations of switches in the input circuit when configured for its normal operating mode.

    摘要翻译： 可编程增益放大器（PGA）包括运算放大器，输入电路，反馈电路和校准电路。 输入电路连接在PGA输入节点和运算放大器输入节点之间，并选择性地将模拟输入信号应用于运算放大器输入节点。 反馈电路连接在运算放大器输出节点和运算放大器输入节点之间，并将放大的模拟输出信号作为反馈信号施加到运算放大器输入节点。 校准电路连接在校准参考节点和运算放大器输入节点之间，并选择性地将校准参考节点直接连接到运算放大器输入节点，而不会跳过任何输入电路。 PGA可以实现为单端或差分放大器。 当配置为正常工作模式时，PGA避免了输入电路中开关串联组合引起的线性度降低。

    Data acquisition system
    7.
    发明授权
    Data acquisition system 有权
    数据采集​​系统

    公开(公告)号：US08643526B1

    公开(公告)日：2014-02-04

    申请号：US13779751

    申请日：2013-02-28

    申请人： Sanjoy K. Dey ,  Ammisetti V. Prasad ,  Mahendra Pal Singh

    发明人： Sanjoy K. Dey ,  Ammisetti V. Prasad ,  Mahendra Pal Singh

    IPC分类号： H03M1/12

    CPC分类号： H03M1/0663 ,  H03F3/387 ,  H03F3/45475 ,  H03M1/12

    摘要： A data acquisition system for converting an analog input signal to a digital output signal includes a programmable gain amplifier (PGA), an analog to digital converter (ADC), and an averaging module. The PGA generates first and second amplified signals during respective first and second conversion cycles. The first and second amplified signals include respective first and second amplified input signals and first and second sets of offset and noise signals. The first and second amplified input signals have the same polarities, and the first and second sets of offset and noise signals have opposite polarities. The ADC generates first and second digital samples corresponding to the first and second amplified signals respectively and the averaging module averages the first and second digital samples to eliminate the first and second sets of offset and noise signals from the digital output signal.

    摘要翻译： 用于将模拟输入信号转换为数字输出信号的数据采集系统包括可编程增益放大器（PGA），模数转换器（ADC）和平均模块。 PGA在相应的第一和第二转换周期期间产生第一和第二放大信号。 第一和第二放大信号包括相应的第一和第二放大输入信号以及第一和第二组偏移和噪声信号。 第一和第二放大的输入信号具有相同的极性，并且第一和第二组偏移和噪声信号具有相反的极性。 ADC分别产生对应于第一和第二放大信号的第一和第二数字采样，并且平均模块对第一和第二数字采样进行平均以消除来自数字输出信号的第一和第二组偏移和噪声信号。