公开(公告)号：US5422300A

公开(公告)日：1995-06-06

申请号：US291781

申请日：1994-08-17

申请人： James R. Pfiester ,  Prashant Kenkare ,  Kent J. Cooper ,  Bich-Yen Nguyen

发明人： James R. Pfiester ,  Prashant Kenkare ,  Kent J. Cooper ,  Bich-Yen Nguyen

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is formed on a silicon substrate (12) and a layer of silicon nitride is then deposited over it. The silicon nitride is subsequently patterned to form a field oxidation mask (18) which defines isolation regions (22) within the silicon substrate (12). Field oxide (34) is grown in the isolation regions (22) of the silicon substrate (12) and the field oxidation mask (18) is subsequently removed.

摘要翻译： 使用热二氧化硅的层叠层（14）和在氮化硅场氧化掩模（18）下方的化学气相沉积二氧化硅来实现无缺陷的场氧化物隔离。 二氧化硅层叠层（14）形成在硅衬底（12）上，然后在其上沉积氮化硅层。 氮化硅随后被图案化以形成限定硅衬底（12）内的隔离区域（22）的场氧化掩模（18）。 场氧化物（34）生长在硅衬底（12）的隔离区（22）中，随后去除场氧化掩模（18）。

公开(公告)号：US5538922A

公开(公告)日：1996-07-23

申请号：US378990

申请日：1995-01-25

申请人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

IPC分类号： H01L21/60 ,  H01L21/46

CPC分类号： H01L21/76897 ,  Y10S148/02 ,  Y10S438/97

摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

摘要翻译： 接触形成在半导体器件（10）中，与底层的形貌或间距无关。 在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。 在绝缘层上沉积蚀刻停止层（20）。 在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。 从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。 绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。 取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

公开(公告)号：US5158898A

公开(公告)日：1992-10-27

申请号：US794279

申请日：1991-11-19

申请人： James D. Hayden ,  Bich-Yen Nguyen ,  Kent J. Cooper

发明人： James D. Hayden ,  Bich-Yen Nguyen ,  Kent J. Cooper

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L21/84 ,  H01L29/78678

摘要： A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

摘要翻译： 一种自对准的下栅极TFT器件（10）。 形成基层（14）。 形成在基底层（14）上方的导电层（16）。 形成在导电层（16）上方的电介质层（18）。 形成覆盖在电介质层（18）上的牺牲层（20）。 层（16,18和20）被蚀刻以形成“柱”区域。 将覆盖在“柱”区域上的电介质层（22）和平面层（24）被回蚀刻以形成基本上平坦的表面并且暴露牺牲层（20）的顶部部分。 去除牺牲层（20），并且形成覆盖导电区域（16）和平面层（22）的导电层（28）。 导电层（28）用于通过形成邻近对准的插塞区域（32）的源区（33）和漏区（34）来形成自对准TFT器件（10）。

公开(公告)号：US5219793A

公开(公告)日：1993-06-15

申请号：US709554

申请日：1991-06-03

申请人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

IPC分类号： H01L21/60

CPC分类号： H01L21/76897 ,  Y10S148/02 ,  Y10S438/97

摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

摘要翻译： 接触形成在半导体器件（10）中，与底层的形貌或间距无关。 在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。 在绝缘层上沉积蚀刻停止层（20）。 在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。 从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。 绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。 取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

公开(公告)号：US5604159A

公开(公告)日：1997-02-18

申请号：US188986

申请日：1994-01-31

申请人： Kent J. Cooper ,  Scott S. Roth

发明人： Kent J. Cooper ,  Scott S. Roth

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/28

摘要： The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.

摘要翻译： 在通过沟槽隔离制造的集成电路中接触半导体器件所需的水平表面积被最小化，而不会通过利用沟槽侧壁的垂直表面积来降低接触电阻。 沟槽隔离区（40）形成在半导体衬底（12）内。 然后形成掺杂区域（74,96），使得其邻接沟槽侧壁（24）。 然后，通过在沟槽隔离区域（40）内形成凹部（55,112）来暴露沟槽侧壁（24）的与掺杂区域（74,96）邻接的部分（56,110）。 然后形成导电构件（66,114,118），使得其沿着暴露的沟槽侧壁以及沿着半导体衬底（12）的主表面（13）电耦合到掺杂区域（74,96） ），并且导致形成低电阻接触结构。

公开(公告)号：US06285073B1

公开(公告)日：2001-09-04

申请号：US08453689

申请日：1995-05-30

申请人： Kent J. Cooper ,  Scott S. Roth

发明人： Kent J. Cooper ,  Scott S. Roth

IPC分类号： H01L2906

CPC分类号： H01L21/28

摘要： The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.

摘要翻译： 在通过沟槽隔离制造的集成电路中接触半导体器件所需的水平表面积被最小化，而不会通过利用沟槽侧壁的垂直表面积来降低接触电阻。 沟槽隔离区（40）形成在半导体衬底（12）内。 然后形成掺杂区域（74,96），使得其邻接沟槽侧壁（24）。 然后，通过在沟槽隔离区域（40）内形成凹部（55,112）来暴露沟槽侧壁（24）的与掺杂区域（74,96）邻接的部分（56,110）。 然后形成导电构件（66,114,118），使得其沿着暴露的沟槽侧壁以及沿着半导体衬底（12）的主表面（13）电耦合到掺杂区域（74,96） ），并且导致形成低电阻接触结构。

公开(公告)号：US5308997A

公开(公告)日：1994-05-03

申请号：US902216

申请日：1992-06-22

申请人： Kent J. Cooper ,  Scott S. Roth ,  James D. Hayden ,  Howard C. Kirsch

发明人： Kent J. Cooper ,  Scott S. Roth ,  James D. Hayden ,  Howard C. Kirsch

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/11 ,  H01L29/417 ,  H01L29/786 ,  H01L29/04 ,  H01L27/01 ,  H01L31/036

CPC分类号： H01L29/78696 ,  H01L27/1108 ,  H01L29/41733 ,  H01L29/66757

摘要： A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).

摘要翻译： 在一个实施例中，通过在覆盖在基板（116）上的电介质层（118）中形成开口（124）来制造具有自对准源区和漏区的薄膜晶体管。 围绕开口（124）的周边（126）并且邻近开口（124）的侧壁（128）形成半导体侧壁间隔物（130）。 第一电极区域（120）在位于开口（124）的仅位于开口的第二侧面半部分（124）的周边（126）的第一位置处电耦合到半导体侧壁间隔件（130）的第一部分 124）。 第二电极区域（122）在位于开口（124）的仅位于开口的第一侧面半部分（124）的周边（126）的第二位置处电连接到半导体侧壁间隔件（130）的第二部分 124）。 邻近半导体侧壁间隔物（130）形成介电层（132）。 与电介质层（132）相邻地形成控制电极（134）。

公开(公告)号：US5210435A

公开(公告)日：1993-05-11

申请号：US745652

申请日：1991-08-16

申请人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

发明人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/7836

摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.

摘要翻译： 一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。 可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。 根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。 第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。 在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。 工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。 工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。 第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。

公开(公告)号：US5485420A

公开(公告)日：1996-01-16

申请号：US278465

申请日：1994-07-21

申请人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

发明人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

IPC分类号： G11C11/412 ,  H01L21/8244 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。

公开(公告)号：US5377139A

公开(公告)日：1994-12-27

申请号：US990341

申请日：1992-12-11

申请人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

发明人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

IPC分类号： G11C11/412 ,  H01L21/8244 ,  G11C13/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。