公开(公告)号：US06762094B2

公开(公告)日：2004-07-13

申请号：US10256984

申请日：2002-09-27

申请人： James Stasiak ,  Jennifer Wu ,  David E Hackleman

发明人： James Stasiak ,  Jennifer Wu ,  David E Hackleman

IPC分类号： H05K336

CPC分类号： H01L29/861 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/8222 ,  H01L27/0766 ,  H01L27/082 ,  H01L27/1021 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0684 ,  H01L29/66272 ,  H01L29/732 ,  Y10S438/961 ,  Y10S438/962 ,  Y10S977/887 ,  Y10T29/49126 ,  Y10T29/49128

摘要： A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.

摘要翻译： 一种半导体器件，包括具有第一极性的掺杂剂的衬底，第一半导体结构，其包括设置在衬底上的第二极性的掺杂剂，并且具有基本平坦的顶表面和侧表面。 半导体器件包括形成在第一半导体结构和衬底之间的第一结，其具有至少一个横向尺寸小于约75纳米的区域。

公开(公告)号：US07833801B2

公开(公告)日：2010-11-16

申请号：US11601062

申请日：2006-11-17

申请人： James Stasiak ,  Paul H. McClelland ,  David E. Hackleman ,  Grant Pease ,  R. Stanley Williams ,  Kevin Peters

发明人： James Stasiak ,  Paul H. McClelland ,  David E. Hackleman ,  Grant Pease ,  R. Stanley Williams ,  Kevin Peters

IPC分类号： G01N33/00

CPC分类号： G01N27/3278 ,  Y10T436/114998

摘要： A sensor device and method for detecting the presence of an analyte in a fluid solution are disclosed. The sensor device system can comprise a substrate and an array of free-standing nanowires attached to the substrate. The array can include individual free-standing nanowires wherein each of the individual free-standing nanowires have a first end and a second end. The first end can, in some embodiments, be attached to the substrate and the second end unattached to the substrate. Such individual free-standing nanowires are configured for electrical communication with other individual free-standing nanowires through the first end. A chip or computer can be electrically coupled to the array of free-standing nanowires for receiving electrical information from the array of free-standing nanowires. In some embodiments a power source can be used to send current through the nanowire array.

摘要翻译： 公开了一种用于检测流体溶液中分析物的存在的传感器装置和方法。 传感器装置系统可以包括衬底和连接到衬底的独立的纳米线阵列。 阵列可以包括单独的独立的纳米线，其中每个独立的纳米线具有第一端和第二端。 在一些实施例中，第一端可以附接到衬底，而第二端可以不附着于衬底。 这种单独的独立的纳米线被配置为通过第一端与其他单独的独立的纳米线电连通。 芯片或计算机可以电耦合到独立的纳米线阵列，用于从独立的纳米线阵列接收电信息。 在一些实施例中，电源可以用于通过纳米线阵列发送电流。

公开(公告)号：US20080204048A1

公开(公告)日：2008-08-28

申请号：US11601062

申请日：2006-11-17

申请人： James Stasiak ,  Paul H. McClelland ,  David E. Hackleman ,  Grant Pease ,  R. Stanley Williams ,  Kevin Peters

发明人： James Stasiak ,  Paul H. McClelland ,  David E. Hackleman ,  Grant Pease ,  R. Stanley Williams ,  Kevin Peters

IPC分类号： G01N27/22 ,  G01N27/02

CPC分类号： G01N27/3278 ,  Y10T436/114998

摘要： A sensor device and method for detecting the presence of an analyte in a fluid solution are disclosed. The sensor device system can comprise a substrate and an array of free-standing nanowires attached to the substrate. The array can include individual free-standing nanowires wherein each of the individual free-standing nanowires have a first end and a second end. The first end can, in some embodiments, be attached to the substrate and the second end unattached to the substrate. Such individual free-standing nanowires are configured for electrical communication with other individual free-standing nanowires through the first end. A chip or computer can be electrically coupled to the array of free-standing nanowires for receiving electrical information from the array of free-standing nanowires. In some embodiments a power source can be used to send current through the nanowire array.

摘要翻译： 公开了一种用于检测流体溶液中分析物的存在的传感器装置和方法。 传感器装置系统可以包括衬底和连接到衬底的独立的纳米线阵列。 阵列可以包括单独的独立的纳米线，其中每个独立的纳米线具有第一端和第二端。 在一些实施例中，第一端可以附接到衬底，而第二端可以不附着于衬底。 这种单独的独立的纳米线被配置为通过第一端与其他单独的独立的纳米线电连通。 芯片或计算机可以电耦合到独立的纳米线阵列，用于从独立的纳米线阵列接收电信息。 在一些实施例中，电源可以用于通过纳米线阵列发送电流。

公开(公告)号：US07163659B2

公开(公告)日：2007-01-16

申请号：US10309608

申请日：2002-12-03

申请人： James Stasiak ,  Paul H McClelland ,  David E Hackleman ,  Grant Pease ,  R. Stanley Williams ,  Kevin Peters

发明人： James Stasiak ,  Paul H McClelland ,  David E Hackleman ,  Grant Pease ,  R. Stanley Williams ,  Kevin Peters

IPC分类号： G01N31/00

CPC分类号： G01N27/3278 ,  Y10T436/114998

摘要： A sensor device and method for detecting the presence of an analyte in a fluid solution are disclosed. The sensor device system can comprise a substrate and an array of free-standing nanowires attached to the substrate. The array can include individual free-standing nanowires wherein each of the individual free-standing nanowires have a first end and a second end. The first end can, in some embodiments, be attached to the substrate and the second end unattached to the substrate. Such individual free-standing nanowires are configured for electrical communication with other individual free-standing nanowires through the first end. A signal measurement apparatus can be electrically coupled to the array of free-standing nanowires for receiving electrical information from the array of free-standing nanowires.

摘要翻译： 公开了一种用于检测流体溶液中分析物的存在的传感器装置和方法。 传感器装置系统可以包括衬底和连接到衬底的独立的纳米线阵列。 阵列可以包括单独的独立的纳米线，其中每个独立的纳米线具有第一端和第二端。 在一些实施例中，第一端可以附接到衬底，而第二端可以不附着于衬底。 这种单独的独立的纳米线被配置为通过第一端与其他单独的独立的纳米线电连通。 信号测量装置可以电耦合到独立的纳米线阵列，用于从独立的纳米线阵列接收电信息。

公开(公告)号：US07034332B2

公开(公告)日：2006-04-25

申请号：US10765799

申请日：2004-01-27

申请人： James Stasiak ,  Kevin F Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

发明人： James Stasiak ,  Kevin F Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

IPC分类号： H01L35/24

CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

摘要： A memory device including a substrate, and multiple self-alignednano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

公开(公告)号：US07335579B2

公开(公告)日：2008-02-26

申请号：US11331697

申请日：2006-01-12

申请人： James Stasiak ,  Kevin F Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

发明人： James Stasiak ,  Kevin F Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

IPC分类号： H01L21/20

CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

摘要： A memory device including a substrate, and multiple self-aligned nano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

公开(公告)号：US20060128129A1

公开(公告)日：2006-06-15

申请号：US11331697

申请日：2006-01-12

申请人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

发明人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

IPC分类号： H01L21/20

CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

摘要： A memory device including a substrate, and multiple self-aligned nano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

公开(公告)号：US20050162881A1

公开(公告)日：2005-07-28

申请号：US10765799

申请日：2004-01-27

申请人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

发明人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

IPC分类号： H01L21/027 ,  G03F7/00 ,  H01L21/329 ,  H01L21/8229 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/102 ,  H01L27/105 ,  H01L27/24 ,  H01L27/28 ,  H01L51/05 ,  G11C5/06

CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

摘要： A memory device including a substrate, and multiple self-alignednano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

公开(公告)号：US20070034909A1

公开(公告)日：2007-02-15

申请号：US11586254

申请日：2006-10-24

申请人： James Stasiak ,  Jennifer Wu ,  David Hackleman

发明人： James Stasiak ,  Jennifer Wu ,  David Hackleman

IPC分类号： H01L29/80

CPC分类号： H01L29/7308 ,  B82Y10/00 ,  H01L27/10

摘要： A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.

摘要翻译： 一种半导体器件，包括具有第一极性的掺杂剂的衬底，第一半导体结构，其包括设置在衬底上的第二极性的掺杂剂，并且具有基本平坦的顶表面和侧表面。 半导体器件包括形成在第一半导体结构和衬底之间的第一结，其具有至少一个横向尺寸小于约75纳米的区域。

公开(公告)号：US20110159648A1

公开(公告)日：2011-06-30

申请号：US13040401

申请日：2011-03-04

申请人： Adam L. Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen H. Kawamoto

发明人： Adam L. Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen H. Kawamoto

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/823437 ,  H01L29/1033 ,  H01L29/66575

摘要： A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

摘要翻译： 纳米晶体管通过在半导体衬底上形成氧化物层，施加抗蚀剂，使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案，在图案上施加第一离子掩模材料，选择性地将其提升到 留下第一离子掩模以形成栅极，通过注入合适的掺杂剂形成掺杂区域，施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案，施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模，以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。