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    Methods of fomring array of nanoscopic MOSFET transistors
    1.
    发明授权
    Methods of fomring array of nanoscopic MOSFET transistors 有权
    制造纳米级MOSFET晶体管阵列的方法

    公开(公告)号：US08329527B2

    公开(公告)日：2012-12-11

    申请号：US13040401

    申请日：2011-03-04

    申请人： Adam L Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen H. Kawamoto

    发明人： Adam L Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen H. Kawamoto

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/823437 ,  H01L29/1033 ,  H01L29/66575

    摘要： A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

    摘要翻译： 纳米晶体管通过在半导体衬底上形成氧化物层，施加抗蚀剂，使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案，在图案上施加第一离子掩模材料，选择性地将其提升到 留下第一离子掩模以形成栅极，通过注入合适的掺杂剂形成掺杂区域，施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案，施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模，以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。

    Array of nanoscopic MOSFET transistors and fabrication methods
    2.
    发明授权
    Array of nanoscopic MOSFET transistors and fabrication methods 有权
    纳米MOSFET晶体管阵列及其制造方法

    公开(公告)号：US07902015B2

    公开(公告)日：2011-03-08

    申请号：US11126710

    申请日：2005-05-10

    申请人： Adam L Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen H. Kawamoto

    发明人： Adam L Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen H. Kawamoto

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/823437 ,  H01L29/1033 ,  H01L29/66575

    摘要： A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

    摘要翻译： 纳米晶体管通过在半导体衬底上形成氧化物层，施加抗蚀剂，使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案，在图案上施加第一离子掩模材料，选择性地将其提升到 留下第一离子掩模以形成栅极，通过注入合适的掺杂剂形成掺杂区域，施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案，施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模，以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。

    Memory device having a semiconducting polymer film
    3.
    发明授权
    Memory device having a semiconducting polymer film 失效
    具有半导体聚合物膜的存储器件

    公开(公告)号：US07612369B2

    公开(公告)日：2009-11-03

    申请号：US11223219

    申请日：2005-09-09

    申请人： James Stasiak

    发明人： James Stasiak

    IPC分类号： H01L29/08

    CPC分类号： G11C11/34 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/28 ,  H01L27/285 ,  H01L51/0042 ,  H01L51/005 ,  H01L51/0078 ,  H01L51/0094 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory device includes a semiconducting polymer film, which includes an organic dopant. The semiconducting polymer film has a first side and a second side. The memory device also includes a first plurality of electrical conductors substantially parallel to each other coupled to the first side of the semiconducting polymer layer, and a second plurality of electrical conductors substantially parallel to each other, coupled to the second side of the semiconducting polymer layer. The first and second pluralities of electrical conductors are substantially mutually orthogonal to each other. Further, an electrical charge is localized on the organic dopant.

    摘要翻译： 存储器件包括半导体聚合物膜，其包括有机掺杂剂。 半导体聚合物膜具有第一面和第二面。 存储器件还包括彼此平行的第一多个电导体，其耦合到半导体聚合物层的第一侧，以及彼此平行的第二多个电导体，其耦合到半导体聚合物层的第二侧 。 第一和第二多个电导体彼此基本上相互正交。 此外，电荷定位在有机掺杂剂上。

    Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making
    5.
    发明授权
    Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making 失效
    采用自对准整流元件的纳米级存储器件及其制造方法

    公开(公告)号：US07335579B2

    公开(公告)日：2008-02-26

    申请号：US11331697

    申请日：2006-01-12

    申请人： James Stasiak ,  Kevin F Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

    发明人： James Stasiak ,  Kevin F Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

    IPC分类号： H01L21/20

    CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

    摘要： A memory device including a substrate, and multiple self-aligned nano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

    摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

    Photonic Structures, Devices, and Methods
    6.
    发明申请
    Photonic Structures, Devices, and Methods 有权
    光子结构，器件和方法

    公开(公告)号：US20080014353A1

    公开(公告)日：2008-01-17

    申请号：US11774397

    申请日：2007-07-06

    申请人： James Stasiak ,  David Champion ,  Kevin Peters ,  Donald Coulman ,  Tony Cruz-Uribe

    发明人： James Stasiak ,  David Champion ,  Kevin Peters ,  Donald Coulman ,  Tony Cruz-Uribe

    IPC分类号： B05D1/32

    CPC分类号： G02B6/1225 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G03F7/0002

    摘要： Photonic crystal structures are made by a method including steps of providing a substrate, depositing at least one planar layer to form a stack, each planar layer of the stack comprising two or more sublayers having different sublayer refractive indices, depositing a hard mask material, depositing an imprintable material over the hard mask material, patterning the imprintable material by imprinting an array of depressions, and directionally etching at the depressions a regular array of openings through the hard mask material and the stack.

    摘要翻译： 光子晶体结构通过包括提供衬底，沉积至少一个平面层以形成堆叠的步骤的方法制成，堆叠的每个平面层包括具有不同子层折射率的两个或多个子层，沉积硬掩模材料，沉积 在硬掩模材料之上的可压印材料，通过压印凹陷阵列来图案化可压印材料，并且在凹陷处定向蚀刻通过硬掩模材料和叠层的规则的开口阵列。

    Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making
    8.
    发明申请
    Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making 失效
    采用自对准整流元件的纳米级存储器件及其制造方法

    公开(公告)号：US20060128129A1

    公开(公告)日：2006-06-15

    申请号：US11331697

    申请日：2006-01-12

    申请人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

    发明人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

    IPC分类号： H01L21/20

    CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

    摘要： A memory device including a substrate, and multiple self-aligned nano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

    摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

    Array of nanoscopic mosfet transistors and fabrication methods
    9.
    发明申请
    Array of nanoscopic mosfet transistors and fabrication methods 有权
    纳米晶体管阵列和制造方法

    公开(公告)号：US20050219936A1

    公开(公告)日：2005-10-06

    申请号：US11126710

    申请日：2005-05-10

    申请人： Adam Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen Kawamoto

    发明人： Adam Ghozeil ,  James Stasiak ,  Kevin Peters ,  Galen Kawamoto

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H05K7/12

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/823437 ,  H01L29/1033 ,  H01L29/66575

    摘要： A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

    摘要翻译： 纳米晶体管通过在半导体衬底上形成氧化物层，施加抗蚀剂，使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案，在图案上施加第一离子掩模材料，选择性地将其提升到 留下第一离子掩模以形成栅极，通过注入合适的掺杂剂形成掺杂区域，施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案，施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模，以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。