公开(公告)号：US06826827B1

公开(公告)日：2004-12-07

申请号：US09707452

申请日：2000-11-07

申请人： Joseph C. Fjelstad

发明人： Joseph C. Fjelstad

IPC分类号： H05K336

CPC分类号： H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/72 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of fabricating interconnection members for a microelectronic device. An electrically conductive sheet having a uniform thickness is coupled to a first surface of a support substrate. Portions of the conductive sheet are selectively removed so as to leave a plurality of substantially rigid, elongated posts protruding parallel to one another from surface of the support substrate.

摘要翻译： 一种制造用于微电子器件的互连构件的方法。 具有均匀厚度的导电片被耦合到支撑衬底的第一表面。 选择性地去除导电片的部分，以便留下从支撑衬底的表面彼此平行突出的多个基本刚性的细长柱。

公开(公告)号：US06762094B2

公开(公告)日：2004-07-13

申请号：US10256984

申请日：2002-09-27

申请人： James Stasiak ,  Jennifer Wu ,  David E Hackleman

发明人： James Stasiak ,  Jennifer Wu ,  David E Hackleman

IPC分类号： H05K336

CPC分类号： H01L29/861 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/8222 ,  H01L27/0766 ,  H01L27/082 ,  H01L27/1021 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0684 ,  H01L29/66272 ,  H01L29/732 ,  Y10S438/961 ,  Y10S438/962 ,  Y10S977/887 ,  Y10T29/49126 ,  Y10T29/49128

摘要： A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.

摘要翻译： 一种半导体器件，包括具有第一极性的掺杂剂的衬底，第一半导体结构，其包括设置在衬底上的第二极性的掺杂剂，并且具有基本平坦的顶表面和侧表面。 半导体器件包括形成在第一半导体结构和衬底之间的第一结，其具有至少一个横向尺寸小于约75纳米的区域。

公开(公告)号：US06698091B1

公开(公告)日：2004-03-02

申请号：US09752162

申请日：2000-12-29

申请人： Matthew L. Heston ,  James T. Theodoras, II

发明人： Matthew L. Heston ,  James T. Theodoras, II

IPC分类号： H05K336

CPC分类号： H05K3/368 ,  H05K1/141 ,  H05K3/306 ,  H05K2201/096 ,  H05K2201/10303 ,  H05K2201/10325 ,  H05K2201/10424 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49208 ,  Y10T29/53087 ,  Y10T29/53091 ,  Y10T29/53174 ,  Y10T29/53261 ,  Y10T29/53265

摘要： A method and circuit board assembly provide a zero interconnection height in a board-to-board interconnect while maintaining efficient space allocation for multiple axis connections by providing a floating connection in one plane thereby enabling a connection in another plane. A method for interconnecting includes aligning a first circuit board having a first plurality of through-holes with a second circuit board having a second plurality of through-holes by matching the first plurality of through-holes with the second plurality of through-holes, the aligning providing an interconnection height of zero between the first circuit board and the second circuit board, aligning at least one pass-through socket with the aligned combination of the first circuit board and second circuit board, the at least one pass-through socket including pass-through socket through-holes, and inserting one or more pins disposed on a pin header through the at least one pass-through socket, the first circuit board and the second circuit board. The method further includes floating one of the first circuit board and the second circuit board prior to inserting the pin header, the floating enabling the first circuit board to interconnect with the second circuit board with a connector aligned along an axis different from the pin header.

摘要翻译： 方法和电路板组件在板对板互连中提供零互连高度，同时通过在一个平面中提供浮动连接，从而实现另一平面中的连接，同时为多轴连接保持有效的空间分配。 一种用于互连的方法包括：将具有第一多个通孔的第一电路板与具有第二多个通孔的第二电路板对准，该第二电路板具有第一多个通孔与第二多个通孔的匹配， 对准在第一电路板和第二电路板之间提供零的互连高度，使至少一个通孔插座与第一电路板和第二电路板的对准组合对准，所述至少一个穿通插座包括通孔 通过插座通孔，并且通过所述至少一个穿通插座，所述第一电路板和所述第二电路板插入设置在所述插头插头上的一个或多个销。 该方法还包括在插入引脚头之前漂浮第一电路板和第二电路板中的一个，浮动使得第一电路板与第二电路板互连，该连接器沿着与引脚头不同的轴对准。

公开(公告)号：US06640429B2

公开(公告)日：2003-11-04

申请号：US10074899

申请日：2002-02-12

申请人： Masayuki Sasaki

发明人： Masayuki Sasaki

IPC分类号： H05K336

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/002 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0394 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49156 ,  H01L2924/00

摘要： A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dielectric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.

摘要翻译： 多层电路板包括：具有上表面和下表面的绝缘层和布置在绝缘层的上表面和下表面上的布线图案。 铁电层的介电常数大于绝缘层的介电常数，并具有上表面和下表面。 铁电层以绝缘层的上表面和下表面分别与铁电层的上表面和下表面一致的方式设置在绝缘层中。 分别在铁电层的上表面和下表面上形成一对电极膜，以限定并入多层电路板中的电容器。

公开(公告)号：US06564451B2

公开(公告)日：2003-05-20

申请号：US09924900

申请日：2001-08-08

申请人： Shigetoshi Abe ,  Tomoko Kato ,  Yasuo Sato ,  Takashi Itagaki ,  Kenji Matsumoto

发明人： Shigetoshi Abe ,  Tomoko Kato ,  Yasuo Sato ,  Takashi Itagaki ,  Kenji Matsumoto

IPC分类号： H05K336

CPC分类号： H05K3/0094 ,  H05K3/0097 ,  H05K2203/0278 ,  H05K2203/0557 ,  H05K2203/085 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165

摘要： On carrying out a hole filling method for a printed wiring board having an interlayer connection hole, first and second printed wiring boards (1 and 2) are prepared, each of which has the interlayer connection hole. The first printed wiring board is placed on a bottom plate (7). On the first printed wiring board, a first hole guide plate (8) having a first guide hole formed at a position corresponding to the interlayer connection hole of the first printed wiring board is placed in such a manner that the first guide hole is coincident with the interlayer connection hole of the first printed wiring board. A hole filling resin (9) is superposed on the first hole guide plate. On the hole filling resin, a second hole guide plate (10) having a second guide hole formed at a position corresponding to the interlayer connection hole of the second printed wiring board is placed. On the second hole guide plate, the second printed wiring board is placed in such a manner that the interlayer connection hole of the second printed wiring board is coincident with the second guide hole of the second hole guide plate. A top plate (11) is placed on the second printed wiring board to form a stacked assembly which includes the first printed wiring board, the first hole guide plate, the hole filling resin, the second hole guide plate, and the second printed wiring board between the bottom plate and the top plate. The stacked assembly is vacuum-pressed between the bottom plate and the top plate to simultaneously fill the interlayer connection holes of the first and the second printed wiring boards with a part of the hole filling resin.

公开(公告)号：US06499213B2

公开(公告)日：2002-12-31

申请号：US09766743

申请日：2001-01-22

申请人： Patrick W. Tandy

发明人： Patrick W. Tandy

IPC分类号： H05K336

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2225/06555 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49144 ,  Y10T29/53174

摘要： A technique for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The technique involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine. In some embodiments, the larger die is affixed to the support structure first and in other embodiments, the smaller die is affixed to the larger die first.

摘要翻译： 用于组装多芯片模块的技术不需要多于一次通过芯片连接机器。 该技术涉及将较小的管芯连接到更大的管芯上而不使用管芯附着机器。 较大的模具可以使用模片连接机器附接到支撑结构。 在一些实施例中，较大的模具首先固定到支撑结构，并且在其他实施例中，较小的模具首先固定到较大的模具。

公开(公告)号：US06389686B1

公开(公告)日：2002-05-21

申请号：US09726328

申请日：2000-12-01

申请人： Yasuhito Takahashi ,  Yasunaga Kurokawa ,  Kenji Iida ,  Masaru Sumi ,  Yuichiro Ohta ,  Toshiro Katsube ,  Kazuo Nakano ,  Norikazu Ozaki ,  Hiroyuki Katayama

发明人： Yasuhito Takahashi ,  Yasunaga Kurokawa ,  Kenji Iida ,  Masaru Sumi ,  Yuichiro Ohta ,  Toshiro Katsube ,  Kazuo Nakano ,  Norikazu Ozaki ,  Hiroyuki Katayama

IPC分类号： H05K336

摘要： A process for fabricating thin multi-layer circuit boards. A substrate is disposed over a heat-accumulating block adjacent thereto so that it is uniformly heated from the back side thereof during the pre-baking.

公开(公告)号：US06378199B1

公开(公告)日：2002-04-30

申请号：US09222988

申请日：1998-12-22

申请人： Hiroto Yoshinuma ,  Kenzaburo Kawai ,  Shinichi Kobayashi

发明人： Hiroto Yoshinuma ,  Kenzaburo Kawai ,  Shinichi Kobayashi

IPC分类号： H05K336

CPC分类号： H05K3/0023 ,  H05K1/095 ,  H05K3/143 ,  H05K3/182 ,  H05K3/184 ,  H05K3/205 ,  H05K3/225 ,  H05K3/325 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/049 ,  H05K2203/0528 ,  H05K2203/0551 ,  H05K2203/0726 ,  H05K2203/107 ,  H05K2203/1105 ,  H05K2203/1115 ,  H05K2203/135 ,  H05K2203/173 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A multi-layer printed-wiring board including a substrate having a plurality of wiring pattern layers sequentially transferred thereon, each wiring pattern layer containing an electrically conductive layer and an electrically insulating layer. The wiring pattern layers are attached to the substrate through an electrically insulating layer.

摘要翻译： 一种多层印刷电路板，包括具有顺序转印在其上的多个布线图案层的基板，每个布线图案层包含导电层和电绝缘层。 布线图案层通过电绝缘层附着到基板上。

公开(公告)号：US06197208B1

公开(公告)日：2001-03-06

申请号：US09214665

申请日：1999-01-07

申请人： Thomas Wiesa

发明人： Thomas Wiesa

IPC分类号： H05K336

CPC分类号： H05K1/148 ,  H05K1/141 ,  H05K1/142 ,  H05K3/0041 ,  H05K3/361 ,  H05K3/363 ,  H05K3/4092 ,  H05K2201/0154

摘要： A method for contacting at least one printed circuit board or at least one punched grid and at least one hybrid includes the steps of: forming contact elements in a contacting foil, positioning the contacting foil over the hybrid in such a way that the contact elements are arranged at preselected positions between the printed circuit traces of the hybrid and the printed circuit traces of the printed circuit board, and etching away at least a portion of the contacting foil, such that the contact elements are at least partially freely accessible.

摘要翻译： 用于接触至少一个印刷电路板或至少一个冲孔格栅和至少一个混合物的方法包括以下步骤：在接触箔中形成接触元件，将接触箔定位在混合物上，使得接触元件为 布置在混合物的印刷电路迹线和印刷电路板的印刷电路迹线之间的预选位置处，并蚀刻掉接触箔的至少一部分，使得接触元件至少部分地可自由接近。

公开(公告)号：US06708400B2

公开(公告)日：2004-03-23

申请号：US09978341

申请日：2001-10-15

申请人： Mark Kintis ,  Charles G. Turner

发明人： Mark Kintis ,  Charles G. Turner

IPC分类号： H05K336

CPC分类号： H05K3/0061 ,  H05K1/0237 ,  H05K3/303 ,  H05K3/341 ,  H05K2201/10371 ,  H05K2203/0173 ,  H05K2203/0278 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  Y10T29/49144 ,  Y10T29/5313 ,  Y10T29/53252 ,  Y10T29/53961

摘要： Reflow soldering of a variety of circuit boards (9, 11, 15) in a variety of sizes and shapes to assigned locations on the base or carrier (13) of the electronic module housing (3) is simplified by eliminating custom made metal blocks previously used to clamp the circuit boards against the carrier metal. Instead, the solder-backed circuit boards are placed in assigned positions in the module housing and the inside volume of that housing is filled (22) with particulate, such as small beads (17), covering the circuit boards, but leaving the edges of the upstanding metal shields (5 and 7) visible. A plate (21) backed foam sheet (19) is placed over the module housing (24) and clamped down (26), pressing against the beads. The clamped assembly is then heated (28) to reflow the solder, soldering the circuit boards in place.

摘要翻译： 通过消除以前定制的金属块，简化了各种尺寸和形状的各种电路板（9,11,15）的回流焊接到电子模块外壳（3）的底座或托架（13）上的指定位置 用于将电路板夹在载体金属上。 相反，焊料背衬的电路板被放置在模块壳体中的分配位置中，并且该壳体的内部体积被填充（22），其具有覆盖电路板的颗粒，例如小珠（17），但是留下边缘 直立的金属屏蔽（5和7）可见。 将板（21）背衬的泡沫板（19）放置在模块壳体（24）上并且被夹紧（26），压靠珠子。 然后将夹紧的组件加热（28）以回流焊料，将电路板焊接到位。