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    Multiple threshold voltage FET using multiple work-function gate materials
    1.
    发明授权
    Multiple threshold voltage FET using multiple work-function gate materials 失效
    多阈值电压FET采用多功能栅极材料

    公开(公告)号：US06448590B1

    公开(公告)日：2002-09-10

    申请号：US09695199

    申请日：2000-10-24

    申请人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    发明人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    IPC分类号： H01L2710

    CPC分类号： H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

    摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

    摘要翻译： 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

    Method for making multiple threshold voltage FET using multiple work-function gate materials
    2.
    发明授权
    Method for making multiple threshold voltage FET using multiple work-function gate materials 有权
    使用多功能栅极材料制造多个阈值电压FET的方法

    公开(公告)号：US06797553B2

    公开(公告)日：2004-09-28

    申请号：US10205143

    申请日：2002-07-24

    申请人： James W Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    发明人： James W Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    IPC分类号： H01L218238

    CPC分类号： H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

    摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

    摘要翻译： 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

    Vertical trench-formed dual-gate FET device structure and method for creation
    3.
    发明授权
    Vertical trench-formed dual-gate FET device structure and method for creation 失效
    垂直沟槽形双栅FET器件结构及其制作方法

    公开(公告)号：US06406962B1

    公开(公告)日：2002-06-18

    申请号：US09761931

    申请日：2001-01-17

    申请人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

    发明人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L21336

    CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78642

    摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

    摘要翻译： 本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有 多个可选择的栅极长度。 本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。 具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点 由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。 附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。

    Out of the box vertical transistor for eDRAM on SOI
    6.
    发明授权
    Out of the box vertical transistor for eDRAM on SOI 有权
    在SOI上用于eDRAM的开箱式垂直晶体管

    公开(公告)号：US07009237B2

    公开(公告)日：2006-03-07

    申请号：US10709450

    申请日：2004-05-06

    申请人： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

    摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

    摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

    Patterned strained semiconductor substrate and device
    9.
    发明授权
    Patterned strained semiconductor substrate and device 有权
    图形应变半导体衬底和器件

    公开(公告)号：US09515140B2

    公开(公告)日：2016-12-06

    申请号：US12015272

    申请日：2008-01-16

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8234

    CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

    摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

    摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

    Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates
    10.
    发明授权
    Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates 有权
    用于在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构

    公开(公告)号：US08703552B2

    公开(公告)日：2014-04-22

    申请号：US13419624

    申请日：2012-03-14

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L27/06 ,  H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181

    摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

    摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。