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    Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same
    2.
    发明申请
    Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same 审中-公开
    在栅极图案上具有至少一个电阻图案的闪存及其制造方法

    公开(公告)号：US20060138559A1

    公开(公告)日：2006-06-29

    申请号：US11317595

    申请日：2005-12-23

    申请人： Dong-Jun Lee ,  Keon-Soo Kim ,  Hyun-Chul Back ,  Seong-Soon Cho

    发明人： Dong-Jun Lee ,  Keon-Soo Kim ,  Hyun-Chul Back ,  Seong-Soon Cho

    IPC分类号： H01L29/00 ,  H01L21/8234

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543

    摘要： Flash memories and methods of manufacturing the same provide at least one resistance pattern on a gate pattern, and are capable of increasing a process margin in the semiconductor fabrication process. Gate patterns and bit line patterns are sequentially formed in a cell array region and a peripheral circuit region of a semiconductor substrate. A bit line interlayer insulating layer is disposed to cover the bit line patterns. At least one resistance pattern is disposed on the bit line interlayer insulating layer in the cell array region of the semiconductor substrate. A planarized interlayer insulating layer is formed on the bit line interlayer insulating layer to cover the resistance pattern. Interconnection lines such as metal interconnection lines are formed on the planarized interlayer insulating layer in the cell array region and the peripheral circuit region of the semiconductor substrate.

    摘要翻译： 闪存及其制造方法在栅极图案上提供至少一个电阻图案，并且能够增加半导体制造工艺中的工艺裕度。 栅极图案和位线图案依次形成在半导体衬底的单元阵列区域和外围电路区域中。 布置位线层间绝缘层以覆盖位线图形。 在半导体衬底的单元阵列区域中的位线层间绝缘层上设置至少一个电阻图案。 平面化层间绝缘层形成在位线层间绝缘层上以覆盖电阻图形。 互连线如金属互连线形成在电池阵列区域和半导体衬底的外围电路区域的平坦化层间绝缘层上。

    Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same
    3.
    发明授权
    Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same 有权
    半导体存储器件包括在隔离栅侧壁上的双重间隔物，包括该隔离栅的电子器件

    公开(公告)号：US07671400B2

    公开(公告)日：2010-03-02

    申请号：US12133587

    申请日：2008-06-05

    申请人： Joon-Sung Lim ,  Jong-Ho Park ,  Hyun-Chul Back ,  Sung-Hun Lee

    发明人： Joon-Sung Lim ,  Jong-Ho Park ,  Hyun-Chul Back ,  Sung-Hun Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.

    摘要翻译： 半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。 浮动门设置在活动区域​​上。 控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。 控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。 第一间隔件设置在相邻浮动门的侧壁上。 每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。 第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。 还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME 有权
    半导体存储器件，其中包括在平板门，包括它们的电子器件上的双重间隔

    公开(公告)号：US20090096005A1

    公开(公告)日：2009-04-16

    申请号：US12133587

    申请日：2008-06-05

    申请人： Joon-Sung LIM ,  Jong-Ho PARK ,  Hyun-Chul BACK ,  Sung-Hun LEE

    发明人： Joon-Sung LIM ,  Jong-Ho PARK ,  Hyun-Chul BACK ,  Sung-Hun LEE

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.

    摘要翻译： 半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。 浮动门设置在活动区域​​上。 控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。 控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。 第一间隔件设置在相邻浮动门的侧壁上。 每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。 第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。 还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。