公开(公告)号：US20170229179A1

公开(公告)日：2017-08-10

申请号：US15501247

申请日：2015-08-06

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY ,  KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY

Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Shuichiro Yamamoto

IPC: G11C14/00 ,  G11C11/16 ,  G11C11/419

CPC classification number: G11C14/0081 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/412 ,  G11C11/419

Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

公开(公告)号：US09496037B2

公开(公告)日：2016-11-15

申请号：US14546668

申请日：2014-11-18

Applicant: Japan Science and Technology Agency

Inventor： Shuichiro Yamamoto ,  Yusuke Shuto ,  Satoshi Sugahara

IPC: G11C14/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C14/0081 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0069 ,  G11C14/0054 ,  G11C2013/0076 ,  G11C2207/2263

Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.

Abstract translation: 存储电路包括：写入数据的双稳态电路（30）; 非易失性元件（MTJ1，MTJ2），以非挥发性方式将写入双稳态电路的数据存储到非易失性元件中，并将以非易失性方式存储的数据恢复到双稳态电路中; 以及当双稳态电路中的数据与非易失性元件中的数据相同时，不将写在双稳态电路中的数据存储到非易失性元件中的确定单元（50），而是将双稳态电路中的数据存储到 当双稳态电路中的数据与非易失性元件中的数据不同时，非易失性元件。

公开(公告)号：US09601198B2

公开(公告)日：2017-03-21

申请号：US14543487

申请日：2014-11-17

Applicant: Japan Science and Technology Agency

Inventor： Yusuke Shuto ,  Shuichiro Yamamoto ,  Satoshi Sugahara

IPC: G11C14/00

CPC classification number: G11C14/0081 ,  G11C11/1675 ,  G11C11/1693

Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

公开(公告)号：US20150070975A1

公开(公告)日：2015-03-12

申请号：US14546668

申请日：2014-11-18

Applicant: Japan Science and Technology Agency

Inventor： Shuichiro Yamamoto ,  Yusuke Shuto ,  Satoshi Sugahara

IPC: G11C14/00

CPC classification number: G11C14/0081 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0069 ,  G11C14/0054 ,  G11C2013/0076 ,  G11C2207/2263

Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.

Abstract translation: 存储电路包括：写入数据的双稳态电路（30）; 非易失性元件（MTJ1，MTJ2），以非挥发性方式将写入双稳态电路的数据存储到非易失性元件中，并将以非易失性方式存储的数据恢复到双稳态电路中; 以及当双稳态电路中的数据与非易失性元件中的数据相同时，不将写在双稳态电路中的数据存储到非易失性元件中的确定单元（50），而是将双稳态电路中的数据存储到 当双稳态电路中的数据与非易失性元件中的数据不同时，非易失性元件。

公开(公告)号：US10049740B2

公开(公告)日：2018-08-14

申请号：US15501247

申请日：2015-08-06

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY ,  KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY

Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Shuichiro Yamamoto

IPC: G11C11/00 ,  G11C14/00 ,  G11C11/419 ,  G11C11/16

Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

公开(公告)号：US09842992B2

公开(公告)日：2017-12-12

申请号：US15125840

申请日：2015-03-06

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Minoru Kurosawa ,  Hiroshi Funakubo ,  Shuichiro Yamamoto

IPC: H01L49/00 ,  H01L27/24 ,  H03K3/356 ,  G11C14/00 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L49/00 ,  G11C11/16 ,  G11C14/0081 ,  G11C14/009 ,  H01L27/226 ,  H01L27/2436 ,  H03K3/356

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

公开(公告)号：US20170005265A1

公开(公告)日：2017-01-05

申请号：US15125840

申请日：2015-03-06

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Minoru Kurosawa ,  Hiroshi Funakubo ,  Shuichiro Yamamoto

IPC: H01L49/00 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L49/00 ,  G11C11/16 ,  G11C14/0081 ,  G11C14/009 ,  H01L27/226 ,  H01L27/2436 ,  H03K3/356

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract translation: 晶体管包括：载流子通过其传导的压电电阻; 将载流子注入压电电阻器的源; 从压电电阻接收载流子的漏极; 定位成围绕压电电阻并向压敏电阻施加压力的压电材料; 以及向压电材料施加电压使得压电材料向压电电阻施加压力的栅极。

公开(公告)号：US20150070974A1

公开(公告)日：2015-03-12

申请号：US14543487

申请日：2014-11-17

Applicant: Japan Science and Technology Agency

Inventor： Yusuke Shuto ,  Shuichiro Yamamoto ,  Satoshi Sugahara

IPC: G11C14/00

CPC classification number: G11C14/0081 ,  G11C11/1675 ,  G11C11/1693

Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

Abstract translation: 存储电路包括：存储数据的双稳态电路（30）; 以非挥发性方式存储写在双稳态电路中的数据的非易失性元件（MTJ1，MTJ2），将以非易失性方式存储的数据恢复到双稳态电路中; 以及控制单元，其以非易失性方式存储写入双稳态电路中的数据，并且当不从双稳态电路读取数据或将数据写入双稳态电路的时间长于预定时间段时，切断对双稳态电路的电源，并且 不以非易失性方式存储写入双稳态电路中的数据，并且当不读或写数据的周期是双稳态电路的电源电压低于该周期期间的电压以从数据读取数据或将数据写入双稳态电路 比预定时间段短。