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公开(公告)号：US09601198B2
公开(公告)日：2017-03-21
申请号：US14543487
申请日：2014-11-17
Applicant: Japan Science and Technology Agency
Inventor： Yusuke Shuto , Shuichiro Yamamoto , Satoshi Sugahara
IPC: G11C14/00
CPC classification number: G11C14/0081 , G11C11/1675 , G11C11/1693
Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.
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公开(公告)号：US20150070975A1
公开(公告)日：2015-03-12
申请号：US14546668
申请日：2014-11-18
Applicant: Japan Science and Technology Agency
Inventor： Shuichiro Yamamoto , Yusuke Shuto , Satoshi Sugahara
IPC: G11C14/00
CPC classification number: G11C14/0081 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C13/0069 , G11C14/0054 , G11C2013/0076 , G11C2207/2263
Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.
Abstract translation: 存储电路包括：写入数据的双稳态电路（30）; 非易失性元件（MTJ1，MTJ2），以非挥发性方式将写入双稳态电路的数据存储到非易失性元件中，并将以非易失性方式存储的数据恢复到双稳态电路中; 以及当双稳态电路中的数据与非易失性元件中的数据相同时，不将写在双稳态电路中的数据存储到非易失性元件中的确定单元（50），而是将双稳态电路中的数据存储到 当双稳态电路中的数据与非易失性元件中的数据不同时，非易失性元件。
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公开(公告)号：US20250069651A1
公开(公告)日：2025-02-27
申请号：US18947451
申请日：2024-11-14
Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor： Satoshi Sugahara , Yusaku Shiotsu
IPC: G11C11/412 , G11C11/419 , H03K3/3565 , H10B10/00
Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.
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公开(公告)号：US12165697B2
公开(公告)日：2024-12-10
申请号：US17536493
申请日：2021-11-29
Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor： Satoshi Sugahara , Daiki Kitagata , Shuichiro Yamamoto
IPC: G11C11/412 , G11C11/418 , G11C11/419 , G11C11/56 , G11C14/00 , H03K3/356
Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.
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公开(公告)号：US09496037B2
公开(公告)日：2016-11-15
申请号：US14546668
申请日：2014-11-18
Applicant: Japan Science and Technology Agency
Inventor： Shuichiro Yamamoto , Yusuke Shuto , Satoshi Sugahara
CPC classification number: G11C14/0081 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C13/0069 , G11C14/0054 , G11C2013/0076 , G11C2207/2263
Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.
Abstract translation: 存储电路包括：写入数据的双稳态电路（30）; 非易失性元件（MTJ1，MTJ2），以非挥发性方式将写入双稳态电路的数据存储到非易失性元件中，并将以非易失性方式存储的数据恢复到双稳态电路中; 以及当双稳态电路中的数据与非易失性元件中的数据相同时，不将写在双稳态电路中的数据存储到非易失性元件中的确定单元（50），而是将双稳态电路中的数据存储到 当双稳态电路中的数据与非易失性元件中的数据不同时，非易失性元件。
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Patent Agency Ranking
公开(公告)号：US12183392B2
公开(公告)日：2024-12-31
申请号：US17877452
申请日：2022-07-29
Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor： Satoshi Sugahara , Yusaku Shiotsu
IPC: G11C11/00 , G11C11/412 , G11C11/419 , H03K3/3565 , H10B10/00
Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.
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公开(公告)号：US20240114791A1
公开(公告)日：2024-04-04
申请号：US18276326
申请日：2022-02-15
Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor： Satoshi Sugahara , Hayato Kumagai
Abstract: A thermoelectric conversion device includes thermoelectric layers and connection layers that are alternately provided in a first direction parallel to surfaces of the thermoelectric layers, and are connected to each other, thermally conductive layers that are connected to the respective connection layers, and extends in a second direction intersecting the surfaces, a first insulating layer that has a smaller thermal conductivity than the thermally conductive layers, and a second insulating layer that has a smaller thermal conductivity than the first insulating layer, is provided between the first insulating layer and the thermoelectric layers, and has a thickness equal to or greater than ¼ of a distance between an end of the thermally conductive layer at a side of one of the thermoelectric layers and a center of another of the connection layers in the first direction, the thermally conductive layers penetrating through the first and second insulating layers.
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公开(公告)号：US20170229179A1
公开(公告)日：2017-08-10
申请号：US15501247
申请日：2015-08-06
Inventor： Satoshi Sugahara , Yusuke Shuto , Shuichiro Yamamoto
IPC: G11C14/00 , G11C11/16 , G11C11/419
CPC classification number: G11C14/0081 , G11C11/1675 , G11C11/1697 , G11C11/412 , G11C11/419
Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.
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公开(公告)号：US20220084583A1
公开(公告)日：2022-03-17
申请号：US17536493
申请日：2021-11-29
Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor： Satoshi Sugahara , Daiki Kitagata , Shuichiro Yamamoto
IPC: G11C11/412 , H03K3/356 , G11C11/419 , G11C11/418
Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.
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公开(公告)号：US10355676B2
公开(公告)日：2019-07-16
申请号：US15558059
申请日：2016-03-24
Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor： Satoshi Sugahara , Shuichiro Yamamoto
IPC: H03K3/037 , H03K3/3565 , G11C11/412 , G11C11/413 , H03K3/356 , H02M7/42 , G11C14/00 , H03K3/0233 , G11C5/14
Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.
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