公开(公告)号：US08836394B2

公开(公告)日：2014-09-16

申请号：US13523631

申请日：2012-06-14

申请人： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

发明人： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC分类号： H03L7/00 ,  H04L7/00 ,  H04L7/033 ,  G11C7/10

CPC分类号： H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

摘要翻译： 在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。 芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

公开(公告)号：US20130249612A1

公开(公告)日：2013-09-26

申请号：US13523631

申请日：2012-06-14

申请人： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

发明人： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC分类号： H03L7/00

CPC分类号： H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

摘要翻译： 在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。 芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

公开(公告)号：US08743973B2

公开(公告)日：2014-06-03

申请号：US13115838

申请日：2011-05-25

申请人： Lei Luo ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Barry W. Daly ,  Wayne D. Dettloff ,  John C. Eble, III ,  John Wilson

发明人： Lei Luo ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Barry W. Daly ,  Wayne D. Dettloff ,  John C. Eble, III ,  John Wilson

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H04L5/20

摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.

摘要翻译： 接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。 接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。 第一和第二电阻元件各自连接在相应接口的输入节点之间。 第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。 中间节点连接到交流接地。 接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入以及输出，以提供从在输入节点处接收的信号的共模分量得到的信号。

公开(公告)号：US20110293041A1

公开(公告)日：2011-12-01

申请号：US13115838

申请日：2011-05-25

申请人： Lei Luo ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Barry W. Daly ,  Wayne D. Dettloff ,  John C. Eble, III ,  John Wilson

发明人： Lei Luo ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Barry W. Daly ,  Wayne D. Dettloff ,  John C. Eble, III ,  John Wilson

IPC分类号： H04L27/00

CPC分类号： H04L5/20

摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.

摘要翻译： 接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。 接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。 第一和第二电阻元件各自连接在相应接口的输入节点之间。 第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。 中间节点连接到交流接地。 接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入端和输出端，以提供从在输入节点接收的信号的共模分量得到的信号。

公开(公告)号：US08279976B2

公开(公告)日：2012-10-02

申请号：US12739938

申请日：2008-10-28

申请人： Qi Lin ,  Hae-Chang Lee ,  Jaeha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

发明人： Qi Lin ,  Hae-Chang Lee ,  Jaeha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

IPC分类号： H03K9/00

CPC分类号： H04L25/0272 ,  H04L5/20 ,  H04L25/0262

摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

摘要翻译： 数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。 第一和第二相应的传输线包括数据接收器电路外部的一对传输线。 第一和第二接口从一对传输线接收传输信号。 共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。 差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。 提取的数据信号具有与提取的时钟信号的频率相对应的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。 差分模式电路与提取的时钟信号同步。

公开(公告)号：US08159274B2

公开(公告)日：2012-04-17

申请号：US12739936

申请日：2008-10-28

申请人： Qi Lin ,  Jaeha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

发明人： Qi Lin ,  Jaeha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H04L7/0008 ,  H04L7/065 ,  H04L25/0276 ,  H04L25/14

摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

摘要翻译： 数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。 数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。 第一速率是第二速率的倍数，其中倍数大于1。 数据传输电路还包括与符号时钟同步的数据驱动器。 数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。 数据信号和时钟信号同时被驱动到一个或多个传输线上。

公开(公告)号：US20110222594A1

公开(公告)日：2011-09-15

申请号：US13103564

申请日：2011-05-09

申请人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

发明人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC分类号： H04L27/00 ,  H04L27/01

CPC分类号： H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

摘要翻译： 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

公开(公告)号：US08477835B2

公开(公告)日：2013-07-02

申请号：US13103564

申请日：2011-05-09

申请人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

发明人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC分类号： H03H7/30

CPC分类号： H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US20100272215A1

公开(公告)日：2010-10-28

申请号：US12739938

申请日：2008-10-28

申请人： Qi Lin ,  Hae-Chang Lee ,  Jacha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

发明人： Qi Lin ,  Hae-Chang Lee ,  Jacha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

IPC分类号： H04L27/00

CPC分类号： H04L25/0272 ,  H04L5/20 ,  H04L25/0262

摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,—the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

摘要翻译： 数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。 第一和第二相应的传输线包括数据接收器电路外部的一对传输线。 第一和第二接口从一对传输线接收传输信号。 共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。 差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。 所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。 差分模式电路与提取的时钟信号同步。

公开(公告)号：US07949041B2

公开(公告)日：2011-05-24

申请号：US12517274

申请日：2007-12-05

申请人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

发明人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC分类号： H03H7/30

CPC分类号： H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

摘要翻译： 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。