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    Flash memory with controlled wordline width
    1.
    发明授权
    Flash memory with controlled wordline width 失效
    具有受控字线宽度的闪存

    公开(公告)号：US06653190B1

    公开(公告)日：2003-11-25

    申请号：US10023436

    申请日：2001-12-15

    申请人： Jean Y. Yang ,  Kouros Ghandehari ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Dawn M. Hopper ,  Angela T. Hui ,  Scott A. Bell

    发明人： Jean Y. Yang ,  Kouros Ghandehari ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Dawn M. Hopper ,  Angela T. Hui ,  Scott A. Bell

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.

    摘要翻译： 用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。 字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。 将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。 使用光掩模处理硬掩模材料以形成硬掩模。 去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。 使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

    Method of making memory wordline hard mask extension
    2.
    发明授权
    Method of making memory wordline hard mask extension 有权
    制作内存字线硬掩模扩展的方法

    公开(公告)号：US06479348B1

    公开(公告)日：2002-11-12

    申请号：US10109516

    申请日：2002-08-27

    申请人： Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Angela T. Hui

    发明人： Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Angela T. Hui

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.

    摘要翻译： 提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。 在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。 字线材料和硬掩模材料沉积在字线材料上。 光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。 使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。 然后去除图案化的光致抗蚀剂。 硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。 使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

    Memory with disposable ARC for wordline formation
    4.
    发明授权
    Memory with disposable ARC for wordline formation 失效
    具有一次性ARC用于字线形成的记忆

    公开(公告)号：US06620717B1

    公开(公告)日：2003-09-16

    申请号：US10100487

    申请日：2002-03-14

    申请人： Tazrien Kamal ,  Scott A. Bell ,  Kouros Ghandehari ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jean Y. Yang

    发明人： Tazrien Kamal ,  Scott A. Bell ,  Kouros Ghandehari ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jean Y. Yang

    IPC分类号： H01L213205

    CPC分类号： H01L27/11568 ,  H01L21/32139 ,  H01L27/115

    摘要： A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.

    摘要翻译： 一种用于闪速存储器的制造方法包括在半导体衬底上沉积电荷捕获材料并植入第一和第二位线。 字线材料沉积在电荷捕获电介质材料上并沉积硬掩模材料。 沉积一次性抗反射涂层（ARC）材料和光致抗蚀剂材料，然后进行处理以形成图案化的光致抗蚀剂材料和图案化的ARC材料。 加工硬掩模材料以形成图案化的硬掩模材料。 去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏图案化的硬掩模材料或字线材料。 使用图案化的硬掩模材料处理字线材料以形成字线，并且去除图案化的硬掩模材料而不损坏字线或电荷捕获电介质材料。

    Memory manufacturing process using disposable ARC for wordline formation
    5.
    发明授权
    Memory manufacturing process using disposable ARC for wordline formation 失效
    使用一次性ARC进行字线形成的存储器制造过程

    公开(公告)号：US06720133B1

    公开(公告)日：2004-04-13

    申请号：US10126280

    申请日：2002-04-19

    申请人： Mark T. Ramsbey ,  Kouros Ghandehari ,  Tazrien Kamal ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa

    发明人： Mark T. Ramsbey ,  Kouros Ghandehari ,  Tazrien Kamal ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa

    IPC分类号： G03F700

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S430/151

    摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

    摘要翻译： 集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。 在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。 在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。 在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。 防反射涂层是可去除的，而不会损坏电荷捕获材料。 在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

    Method of manufacturing a semiconductor memory with deuterated materials
    6.
    发明授权
    Method of manufacturing a semiconductor memory with deuterated materials 有权
    用氘代材料制造半导体存储器的方法

    公开(公告)号：US06884681B1

    公开(公告)日：2005-04-26

    申请号：US10672093

    申请日：2003-09-26

    申请人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

    发明人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

    IPC分类号： H01L21/336 ,  H01L21/8246

    CPC分类号： H01L27/11568 ,  H01L29/66833

    摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

    摘要翻译： 一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。 植入第一和第二位线，并在完成内存之前形成字线。 在字线之间形成间隔，并且在字线之间形成层间电介质层。 第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

    Semiconductor memory with deuterated materials
    7.
    发明授权
    Semiconductor memory with deuterated materials 有权
    具有氘化材料的半导体存储器

    公开(公告)号：US06670241B1

    公开(公告)日：2003-12-30

    申请号：US10128771

    申请日：2002-04-22

    申请人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

    发明人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L29/66833

    摘要： A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

    摘要翻译： 用于制造MirrorBit（闪存）闪存的器件及其制造方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。 植入第一和第二位线，并在完成内存之前形成字线。 在字线之间形成间隔，并且在字线之间形成层间电介质层。 第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

    Liner for semiconductor memories and manufacturing method therefor
    8.
    发明授权
    Liner for semiconductor memories and manufacturing method therefor 有权
    半导体存储器用衬垫及其制造方法

    公开(公告)号：US06803265B1

    公开(公告)日：2004-10-12

    申请号：US10109234

    申请日：2002-03-27

    申请人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn M. Hopper ,  Pei-Yuan Gao

    发明人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn M. Hopper ,  Pei-Yuan Gao

    IPC分类号： H01L21337

    CPC分类号： H01L27/11568 ,  H01L23/26 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.

    摘要翻译： 集成电路存储器的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 减少的氢，紫外阻挡数据保持衬里覆盖字线和电荷捕获介电层。 与现有技术相比，降低的氢含量降低了电荷损失。 在完成集成电路之前，衬里的表面被处理以阻挡UV光。

    Hard mask spacer for sublithographic bitline
    9.
    发明授权
    Hard mask spacer for sublithographic bitline 有权
    用于亚光刻位线的硬掩模垫片

    公开(公告)号：US06962849B1

    公开(公告)日：2005-11-08

    申请号：US10729732

    申请日：2003-12-05

    申请人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

    发明人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

    摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 在形成过程中使用间隔物来减小存储器中的掩埋位线的尺寸，这适用于存储用于计算机等的数据。 较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。 位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。 以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。 此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。