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    Variable rate DPSK system architecture
    1.
    发明授权
    Variable rate DPSK system architecture 有权
    可变速率DPSK系统架构

    公开(公告)号：US06826371B1

    公开(公告)日：2004-11-30

    申请号：US09595285

    申请日：2000-06-15

    申请人： Jeffery S. Bauch ,  Todd E. Humes ,  James A. Roth

    发明人： Jeffery S. Bauch ,  Todd E. Humes ,  James A. Roth

    IPC分类号： H04B1004

    CPC分类号： H04L27/18

    摘要： A communication system and more particularly to a variable rate differential phase shift keying (DPSK) communication system with minimal hardware that does not have power or performance penalties associated with known DPSK modulation systems is disclosed. The DPSK modulation system in accordance with the present invention includes a transmitter, which includes a carrier signal source, a phase modulator and a DPSK encoder for modulating a carrier signal. The modulated carrier signals may be amplified, for example, in optical communication systems by a rare earth element doped fiber amplifier. The signals are continuously transmitted to a multi-rate receiver through a communication channel, for example, free space. The multi-rate receiver includes a single demodulator, for example, a single optical interferometer, used for multiple integer sub-harmonic data rates which demodulates the modulated signal. The demodulated signals are detected, for example, in optical communication systems by an arrangement of photodiodes, and the detected signals are applied to, for example, a clock and data recovery circuit that is tuned as a function of data rate, for example, by way of a switched filter circuit. The switched filter circuit may include a plurality of low-pass filters that are selected as a function of the data rate. Since the carrier signal is continuously transmitted, a phase reference is available to demodulate all received power and the peak transmitted power is approximately equal to the average transmitted power even at data rates corresponding to bit times that are large compared to the differential time delay of the demodulator.

    摘要翻译： 公开了一种通信系统，更具体地涉及一种具有最小硬件的可变速率差分相移键控（DPSK）通信系统，其具有与已知DPSK调制系统相关联的功率或性能损失。 根据本发明的DPSK调制系统包括发射机，其包括载波信号源，相位调制器和用于调制载波信号的DPSK编码器。 经调制的载波信号可以例如在光通信系统中被稀土元素掺杂光纤放大器放大。 这些信号通过通信信道，例如可用空间，被连续发送到多速率接收机。 多速率接收机包括用于解调调制信号的多个整数次谐波数据速率的单个解调器，例如单个光学干涉仪。 解调的信号例如通过光电二极管的布置在光通信系统中被检测，并且所检测的信号被施加到例如作为数据速率的函数被调谐的时钟和数据恢复电路，例如通过 开关滤波电路的方式。 开关滤波器电路可以包括根据数据速率选择的多个低通滤波器。 由于载波信号被连续传输，相位参考可用于解调所有接收的功率，并且峰值发射功率近似等于平均发送功率，即使在对应于与时钟延迟的差分时间相比较的位时间的数据速率 解调器。

    RFID tag uncoupling one of its antenna ports and methods
    2.
    发明授权
    RFID tag uncoupling one of its antenna ports and methods 有权
    RFID标签解耦其天线端口之一和方法

    公开(公告)号：US07667589B2

    公开(公告)日：2010-02-23

    申请号：US10891894

    申请日：2004-07-14

    申请人： Dimitri C. Desmons ,  Ronald A. Oliver ,  Christopher J. Diorio ,  Todd E. Humes

    发明人： Dimitri C. Desmons ,  Ronald A. Oliver ,  Christopher J. Diorio ,  Todd E. Humes

    IPC分类号： G08B19/00

    CPC分类号： G06K19/07767 ,  G06K19/07749

    摘要： RFID tags have an on-chip antenna and an off-chip antenna. One of the antennas can become uncoupled if the proper signal is received, while the other antenna may still operate. The uncoupled antenna can be the larger one, for example the off-chip antenna. Then the tag can then be read only by the smaller antenna, which effectively reduces the range of the RFID tag, but without disabling it entirely.

    摘要翻译： RFID标签具有片上天线和片外天线。 如果接收到适当的信号，其中一个天线可能会脱耦，而另一个天线仍然可以工作。 非耦合天线可以是较大的天线，例如片外天线。 那么标签然后可以被较小的天线读取，这有效地减少了RFID标签的范围，但是没有完全禁用它。

    Apparatus and method for tuning an optical interferometer
    7.
    发明授权
    Apparatus and method for tuning an optical interferometer 有权
    用于调整光学干涉仪的装置和方法

    公开(公告)号：US06396605B1

    公开(公告)日：2002-05-28

    申请号：US09236981

    申请日：1999-01-26

    申请人： Donald G. Heflinger ,  Jeffrey S. Bauch ,  Todd E. Humes

    发明人： Donald G. Heflinger ,  Jeffrey S. Bauch ,  Todd E. Humes

    IPC分类号： H04B1000

    CPC分类号： H04B10/60

    摘要： An apparatus using an optical signal for actively tuning an optical interferometer without introducing any dither in its optical path length. The apparatus comprises a dither generator, means applying a portion of the dithering signal to the optical signal so as to provide an optical signal having a varying wavelength, an optical interferometer having a path length that is tunable and that responds to the optical signal having a varying wavelength and a path length adjustment drive signal and develops a first interference pattern when said path length is a prescribed value and a second interference pattern when the optical path length is changed, photodetector means responsive to the optical interference pattern and operative to develop an electronic feedback signal when the first interference pattern is not present, and a synchronous detection lock-in amplifier that is responsive to a portion of the dithering signal and the electronic feedback signal and operative to produce the optical path length adjustment drive signal. The drive signal changes the optical path length until it reaches the prescribed value, thereby producing the first interference pattern and tuning the optical interferometer. also a method of using an optical signal for tuning an optical interferometer by adjusting its optical path length without introducing dither into the path length is invented.

    摘要翻译： 一种使用光学信号的装置来主动调谐光学干涉仪，而不会在其光程长度上引入任何抖动。 该装置包括抖动发生器，将抖动信号的一部分应用于光信号，以便提供具有变化波长的光信号;光干涉仪，具有可调谐的路径长度，并响应于具有 变化的波长和路径长度调节驱动信号，并且当所述路径长度是规定值时产生第一干涉图案，并且当光路长度改变时产生第二干涉图案，光电检测器装置响应于光学干涉图案并且可操作地开发电子 当不存在第一干涉图案时的反馈信号;以及同步检测锁定放大器，其响应抖动信号和电子反馈信号的一部分并且可操作以产生光程长度调节驱动信号。 驱动信号改变光路长度直到其达到规定值，从而产生第一干涉图案并调谐光学干涉仪。 本发明还提出了一种通过调整其光程长度而不引入抖动进入路径长度来使用光信号来调谐光干涉仪的方法。

    Schottky junction diode devices in CMOS with multiple wells
    8.
    发明授权
    Schottky junction diode devices in CMOS with multiple wells 有权
    具有多个阱的CMOS中的肖特基结二极管器件

    公开(公告)号：US08759937B2

    公开(公告)日：2014-06-24

    申请号：US11387515

    申请日：2006-03-22

    申请人： Yanjun Ma ,  Ronald A. Oliver ,  Todd E. Humes ,  Jaideep Mavoori

    发明人： Yanjun Ma ,  Ronald A. Oliver ,  Todd E. Humes ,  Jaideep Mavoori

    IPC分类号： H01L27/095 ,  H01L29/872 ,  H01L29/66 ,  H01L27/06

    CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

    摘要： A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

    摘要翻译： 在传统的CMOS工艺中制造了具有改进的性能和多阱结构的肖特基结二极管器件。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括不同掺杂的材料，例如与第一导电类型相反的第二导电类型。 第二口井设置在第一井内。 含金属材料的区域设置在第二阱中以在含金属材料区域和第二阱之间的界面处形成肖特基结。 在一个实施例中，第二井接触设置在第二井的一部分中。

    Adaptive programming of memory circuit including writing data in cells of a memory circuit
    10.
    发明授权
    Adaptive programming of memory circuit including writing data in cells of a memory circuit 有权
    存储器电路的自适应编程包括在存储器电路的单元中写入数据

    公开(公告)号：US07724570B1

    公开(公告)日：2010-05-25

    申请号：US11982277

    申请日：2007-10-31

    申请人： Chad A. Lindhorst ,  Todd E. Humes ,  Alex May ,  Agustinus Sutandi

    发明人： Chad A. Lindhorst ,  Todd E. Humes ,  Alex May ,  Agustinus Sutandi

    IPC分类号： G11C14/00

    CPC分类号： G11C5/145 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/30

    摘要： Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

    摘要翻译： 提供了自适应编程方法和用于存储器件的支持器件架构。 方法包括将字划分成可变长度段。 更具体地，方法包括接收数据字，将字解析成多个写子集，其中写子集的大小取决于数据的值和存储电路特有的约束，以及写数据 在存储器电路的单元中，一次写入子集。 存储器装置包括能够将字解析为多个写子集的数字控制器，其中写子集的长度取决于数据的值和对存储器件特有的约束。