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公开(公告)号：US5560001A
公开(公告)日：1996-09-24
申请号：US534480
申请日：1995-09-27
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译： 用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。 本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应外部引脚的断言。 然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。 中断机制也用于优先考虑外部信号在其他系统中断中的发生。 中断机制确保处理器在总线周期的中间没有停止其时钟。
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2.发明授权
公开(公告)号：US5473767A
公开(公告)日：1995-12-05
申请号：US970576
申请日：1992-11-03
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译： 用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。 本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应外部引脚的断言。 然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。 中断机制也用于优先考虑外部信号在其他系统中断中的发生。 中断机制确保处理器在总线周期的中间没有停止其时钟。
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3.发明授权
公开(公告)号：US5560002A
公开(公告)日：1996-09-24
申请号：US534596
申请日：1995-09-27
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译： 用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。 本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应外部引脚的断言。 然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。 中断机制也用于优先考虑外部信号在其他系统中断中的发生。 中断机制确保处理器在总线周期的中间没有停止其时钟。
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4.发明授权
公开(公告)号：US5918043A
公开(公告)日：1999-06-29
申请号：US874559
申请日：1997-06-13
IPC分类号： G06F1/04 , G06F1/10 , G06F1/26 , G06F11/00 , G06F11/267
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译： 用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。 本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应/断言外部引脚。 然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。 中断机制也用于优先考虑外部信号在其他系统中断中的发生。 中断机制确保处理器在总线周期的中间没有停止其时钟。
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5.发明授权Computer system with power management feature for stopping the internal clock of a microprocessor 失效具有电源管理功能的计算机系统，用于停止微处理器的内部时钟
公开(公告)号：US5657483A
公开(公告)日：1997-08-12
申请号：US534575
申请日：1995-09-27
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译： 用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。 本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应外部引脚的断言。 然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。 中断机制也用于优先考虑外部信号在其他系统中断中的发生。 中断机制确保处理器在总线周期的中间没有停止其时钟。
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6.发明授权Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state 失效用于在低功率状态下工作的集成电路中保持高速缓存一致性的方法和装置
公开(公告)号：US6014751A
公开(公告)日：2000-01-11
申请号：US841858
申请日：1997-05-05
申请人： James P. Kardach , John Horigan , Ravi Eakambaram , Tosaku Nakanishi , Chih-Hung Chung , Borys S. Senyk
发明人： James P. Kardach , John Horigan , Ravi Eakambaram , Tosaku Nakanishi , Chih-Hung Chung , Borys S. Senyk
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , G06F12/0835 , Y02B60/1217 , Y02B60/1221
摘要： A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.
摘要翻译： 描述用于操作集成在降低功耗状态的方法和装置。 该装置包括功率降低逻辑，为了将集成电路置于降低功耗状态，将集成电路中的第一组和第二组功能单元的时钟信号置于门限。 第一组功能单元的特征在于需要在集成电路内执行高速缓存一致性操作。 该装置包括输入，该输入被耦合以通过集成电路外部的另外的设备将指示存储器访问的信号接收到由集成电路可访问的存储器资源。 响应于该信号的断言，功率降低逻辑将时钟信号传播到第一组功能单元，以使得该组功能单元能够执行高速缓存一致性操作，这可能由外部存储器访问所必需 设备。
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7.发明授权System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching 有权用于协调第一和第二处理器之间的切换以及在切换期间协调第一和第二处理器之间的高速缓存一致性的系统公开(公告)号：US06631474B1
公开(公告)日：2003-10-07
申请号：US09476038
申请日：1999-12-31
IPC分类号： G06F126
CPC分类号： G06F1/3293 , G06F1/3203 , G06F12/0815 , G06F12/0831 , G06F2212/1016 , G06F2212/1028 , Y02D10/122 , Y02D10/126 , Y02D10/13
摘要： A computer system includes a first processor, a second processor, and interprocessor communication logic (ICL). The first processor operates at a higher frequency, includes a more advanced micro-architecture, and consumes more power than the second processor. When the computer system is plugged in, the first processor is selected as the primary system processor. When the computer system is powered by a battery, the second processor is selected as the primary system processor. The second processor and the ICL may be integrated together on the same semiconductor chip.
摘要翻译： 计算机系统包括第一处理器，第二处理器和处理器间通信逻辑（ICL）。 第一个处理器工作在更高的频率，包括更先进的微架构，并消耗比第二个处理器更多的电力。 当插入计算机系统时，选择第一个处理器作为主系统处理器。 当计算机系统由电池供电时，选择第二处理器作为主系统处理器。 第二处理器和ICL可以集成在同一半导体芯片上。
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公开(公告)号：US4733368A
公开(公告)日：1988-03-22
申请号：US885822
申请日：1986-07-15
CPC分类号： G06F17/2735 , G06F17/2755 , G06F17/2872 , G06F17/289
摘要： An electronic translator comprises an input device for entering a first word or words, a first memory circuit for storing the first words, a second memory circuit for storing second words equivalent to the first words, an access circuit for addressing the memory circuits to cause retrieval of the first word or words, or alternately the second word or words, and a control circuit for controlling activation of the access circuit. There may be additionally provided a holding circuit for holding one or more of the first words without translation thereof.
摘要翻译： 电子翻译器包括用于输入第一个字的输入装置，用于存储第一个字的第一存储器电路，用于存储与第一个字相当的第二个字的第二存储器电路，用于寻址存储器电路以引起检索的存取电路 的第一个字或第二个字或第二个字，以及一个控制电路，用于控制存取电路的激活。 可以另外提供一种用于保持一个或多个第一个字而不进行翻译的保持电路。
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公开(公告)号：US4443856A
公开(公告)日：1984-04-17
申请号：US282238
申请日：1981-07-10
申请人： Shintaro Hashimoto , Masafumi Morimoto , Tosaku Nakanishi , Hideo Yoshida , Shigenobu Yanagiuchi
发明人： Shintaro Hashimoto , Masafumi Morimoto , Tosaku Nakanishi , Hideo Yoshida , Shigenobu Yanagiuchi
摘要： An electronic translator of a desired sentence in a first language to a desired sentence in a second language includes exemplary sentences and selectable words in both languages to simplify translation, and a voice synthesizer to speak the translated desired sentence.
摘要翻译： 将第一语言的期望句子的电子翻译器以第二种语言的期望句子包括在两种语言中的示例性句子和可选择词语以简化翻译，以及语音合成器来说出翻译的期望句子。
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公开(公告)号：US06735659B1
公开(公告)日：2004-05-11
申请号：US09746086
申请日：2000-12-21
IPC分类号： G06F1314
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for serial communication with a co-processor. In one embodiment, a microprocessor is provided with a CPU core, set of serial interface registers, a serial interface unit, to provide serial communication between a co-processor and the microprocessor. The set of serial interface registers is part of a register file of the CPU core and interrupts are exchanged between the CPU core and the co-processor to allow for reading and writing of data placed in the serial registers of the register file.
摘要翻译： 一种用于与协处理器进行串行通信的方法和装置。 在一个实施例中，微处理器设置有CPU核心，串行接口寄存器集合，串行接口单元，以在协处理器和微处理器之间提供串行通信。 串行接口寄存器组是CPU内核寄存器文件的一部分，CPU核和协处理器之间进行中断交换，以允许对写入寄存器文件串行寄存器的数据进行读写。
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