-
公开(公告)号：US07005334B2
公开(公告)日：2006-02-28
申请号：US10845835
申请日：2004-05-14
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L21/823412 , H01L21/823493 , H01L29/78
摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
摘要翻译： 零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。 这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。 可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与 彼此隔开p型衬底材料的口袋。 在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。
-
公开(公告)号：US07057180B2
公开(公告)日：2006-06-06
申请号：US10604416
申请日：2003-07-18
申请人： John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Stephen V. Kosonocky , Randy W. Mann , Jeffery H. Oppold , Norman J. Rohrer
发明人： John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Stephen V. Kosonocky , Randy W. Mann , Jeffery H. Oppold , Norman J. Rohrer
IPC分类号： G01T1/24
CPC分类号： G11C11/4125
摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.
摘要翻译： 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。
-
3.发明授权Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines 有权提供能够允许位线和字线的金属级分配的多种变化的存储单元的方法公开(公告)号：US07237215B2
公开(公告)日：2007-06-26
申请号：US10904226
申请日：2004-10-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.
摘要翻译： 公开了一种用于提供允许位线和字线的金属级分配的多种变化的存储单元的方法。 存储单元包括两个单元元件。 第一和第二电池元件被相同地加工成金属-1层。 随后在金属层2上的位线和金属层3上的字线处理第一个单元元件。 接下来，第二单元元件用金属层3上的位线和金属层2上的字线进行处理。
-
公开(公告)号：US07613047B2
公开(公告)日：2009-11-03
申请号：US11538945
申请日：2006-10-05
IPC分类号： G11C16/06
CPC分类号： G11C7/067 , G11C7/06 , G11C13/00 , G11C13/004 , G11C2213/79
摘要： The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.
摘要翻译： 本发明的实施例提供了一种用于测量电阻的有效电路和方法的装置，方法等。 提供了一种用于集成电路存储器的感测线驱动器，包括从实验结构接收实验信号的感测节点。 输出设备连接到感测节点，其中输出设备放大实验信号。 此外，分压器连接到感测节点，其中分压器包括第一器件和第二器件。 感测范围由第二设备的操作宽度/电阻范围和/或调整信号控制。 调整信号改变第二器件的栅极到源极电压，并且在多个感测实例上保持恒定的电压。 由于第二设备的操作宽度的变化，感测范围对于每个感测实例是不同的。
-
5.发明申请DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES 有权DENSE寄存器阵列用于启用两个L1和L2锁存器的扫描公开(公告)号：US20120179944A1
公开(公告)日：2012-07-12
申请号：US13004104
申请日：2011-01-11
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.
摘要翻译： 可扫描寄存器阵列结构包括多个单独锁存器，每个锁存器被配置为在正常操作模式下保持一位数组数组。 多个单独锁存器在测试操作模式下在可扫描锁存器对中操作，可扫描锁存器对的第一锁存器包括包括L2锁存器的可扫描锁存器对的L1锁存器和第二锁存器。 测试时钟信号为L1锁存器产生第一时钟脉冲信号A，为L2锁存器产生第二时钟脉冲信号B。 L2锁存器还被配置为在独立于测试时钟信号的B时钟信号的单独激活之后有选择地接收L1数据，使得各个锁存器的扫描输出操作导致观察L1锁存器数据。
-
6.发明申请ANALYSIS TECHNIQUES TO REDUCE SIMULATIONS TO CHARACTERIZE THE EFFECT OF VARIATIONS IN TRANSISTOR CIRCUITS 审中-公开分析技术减少模拟以表征变化对晶体管电路的影响公开(公告)号：US20080126061A1
公开(公告)日：2008-05-29
申请号：US11464014
申请日：2006-08-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.
摘要翻译： 本发明的实施例提供了用于分析技术的方法，计算机程序产品等，以减少模拟以表征晶体管电路中的变化的影响。 在集成电路中模拟晶体管的方法通过将一组并联晶体管减少到单个等效晶体管来开始。 随后模拟等效晶体管，其中仅模拟一部分并联晶体管。 接下来，将集成电路分为通道连接部件，并对通道连接部件进行仿真。 为每种类型的通道连接组件创建一个表格; 并且通过集成电路仿真的结果计算跨芯片变化方程的参数化。 此外，创建表条目，其包括多个晶体管类型，多个独特的晶体管原始图案和/或通过晶体管基元图案中的每一个的路径的数量。
-
公开(公告)号：US20080084760A1
公开(公告)日：2008-04-10
申请号：US11538945
申请日：2006-10-05
IPC分类号： G11C11/34
CPC分类号： G11C7/067 , G11C7/06 , G11C13/00 , G11C13/004 , G11C2213/79
摘要： The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.
摘要翻译： 本发明的实施例提供了一种用于测量电阻的有效电路和方法的装置，方法等。 提供了一种用于集成电路存储器的感测线驱动器，包括从实验结构接收实验信号的感测节点。 输出设备连接到感测节点，其中输出设备放大实验信号。 此外，分压器连接到感测节点，其中分压器包括第一器件和第二器件。 感测范围由第二设备的操作宽度/电阻范围和/或调整信号控制。 调整信号改变第二器件的栅极到源极电压，并且在多个感测实例上保持恒定的电压。 由于第二设备的操作宽度的变化，感测范围对于每个感测实例是不同的。
-
公开(公告)号：US6002633A
公开(公告)日：1999-12-14
申请号：US225075
申请日：1999-01-04
CPC分类号： G11C8/12
摘要： A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
摘要翻译： 一种用于构建至少一个可编译SRAM（包括至少一个可编译子块）的编译器。 全局控制时钟产生电路产生全局控制信号。 至少一个本地控制逻辑和速度控制电路控制该至少一个可编译子块。 本地控制逻辑和速度控制电路由全局控制信号控制。 算法接收SRAM阵列的子块的输入容量和配置。 算法确定创建输入容量的子块所需的字数和位线数。 算法通过基于子块中的字线和位线的数量确定全局控制时钟电路来优化子块的周期时间。 算法通过基于字线和位线的数量确定本地速度控制电路来优化子块的访问时间。
-
9.发明授权Dense register array for enabling scan out observation of both L1 and L2 latches 有权密码寄存器阵列，用于扫描L1和L2锁存器的观察公开(公告)号：US08423844B2
公开(公告)日：2013-04-16
申请号：US13004104
申请日：2011-01-11
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.
摘要翻译： 可扫描寄存器阵列结构包括多个单独锁存器，每个锁存器被配置为在正常操作模式下保持一位数组数组。 多个单独的锁存器在测试操作模式下以可扫描的锁存器对操作，可扫描锁存器对的第一锁存器包括包括L2锁存器的可扫描锁存器对的L1锁存器和第二锁存器。 测试时钟信号为L1锁存器产生第一时钟脉冲信号A，为L2锁存器产生第二时钟脉冲信号B。 L2锁存器还被配置为在独立于测试时钟信号的B时钟信号的单独激活之后有选择地接收L1数据，使得各个锁存器的扫描输出操作导致观察L1锁存器数据。
-
10.发明授权公开(公告)号：US07000155B2
公开(公告)日：2006-02-14
申请号：US10249574
申请日：2003-04-21
IPC分类号： G11C29/00
CPC分类号： G11C5/005 , G11C11/4125 , G11C29/787
摘要： A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.022 秒)
