公开(公告)号：US06825530B1

公开(公告)日：2004-11-30

申请号：US10250190

申请日：2003-06-11

申请人： Jeffrey S. Brown ,  Chung H. Lam ,  Randy W. Mann ,  Jeffery H Oppold

发明人： Jeffrey S. Brown ,  Chung H. Lam ,  Randy W. Mann ,  Jeffery H Oppold

IPC分类号： H01L2976

CPC分类号： H01L29/1037 ,  H01L21/823412 ,  H01L21/823493 ,  H01L29/78

摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

摘要翻译： 零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。 这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。 可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与 彼此隔开p型衬底材料的口袋。 在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

公开(公告)号：US07005334B2

公开(公告)日：2006-02-28

申请号：US10845835

申请日：2004-05-14

申请人： Jeffrey S. Brown ,  Chung H. Lam ,  Randy W. Mann ,  Jeffery H. Oppold

发明人： Jeffrey S. Brown ,  Chung H. Lam ,  Randy W. Mann ,  Jeffery H. Oppold

IPC分类号： H01L21/336

CPC分类号： H01L29/1037 ,  H01L21/823412 ,  H01L21/823493 ,  H01L29/78

摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

摘要翻译： 零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。 这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。 可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与 彼此隔开p型衬底材料的口袋。 在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

公开(公告)号：US07057180B2

公开(公告)日：2006-06-06

申请号：US10604416

申请日：2003-07-18

申请人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

发明人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

IPC分类号： G01T1/24

CPC分类号： G11C11/4125

摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.

摘要翻译： 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。

公开(公告)号：US07190007B2

公开(公告)日：2007-03-13

申请号：US10710821

申请日：2004-08-05

申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

IPC分类号： H01L29/47

CPC分类号： H01L21/764 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/78654

摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

摘要翻译： 本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。

公开(公告)号：US06881672B2

公开(公告)日：2005-04-19

申请号：US10723700

申请日：2003-11-26

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/823842

摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

摘要翻译： 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US06815751B2

公开(公告)日：2004-11-09

申请号：US10064301

申请日：2002-07-01

申请人： Jeffrey S. Brown ,  Randy W. Mann

发明人： Jeffrey S. Brown ,  Randy W. Mann

IPC分类号： H01L218234

CPC分类号： H01L27/10861 ,  H01L27/0207 ,  H01L27/1203

摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

公开(公告)号：US06778449B2

公开(公告)日：2004-08-17

申请号：US10064302

申请日：2002-07-01

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Randy W. Mann ,  Jeffrey H. Oppold

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Randy W. Mann ,  Jeffrey H. Oppold

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/5006

摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.

摘要翻译： 用于具有通过导线连接在一起的单元阵列的测试结构的方法和结构。 导线将电池连接在一起，就像它们是单个电池一样。 导线可以包括通用字线; 一个普通的位线 公共位线补码线，公共N阱电压线，公共内部地线，公共内部电压线和/或公共接地线。

公开(公告)号：US06700163B2

公开(公告)日：2004-03-02

申请号：US09683278

申请日：2001-12-07

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC分类号： H01L2976

CPC分类号： H01L21/823871 ,  H01L21/823842

摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

摘要翻译： 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US07087486B2

公开(公告)日：2006-08-08

申请号：US10963228

申请日：2004-10-12

申请人： Jeffrey S. Brown ,  Randy W. Mann

发明人： Jeffrey S. Brown ,  Randy W. Mann

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/0207 ,  H01L27/1203

摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

摘要翻译： 提供了增加电容而不损及电池区的电容器结构及其制造方法。 第一电容器结构包括存在于半导体衬底中的孔中的绝缘材料，其中每个电容器孔的底壁上的绝缘材料与每个孔的侧壁相比较厚。 在另一个电容器结构中，提供深电容器孔，其具有存在于每个孔下方的隔离植入区。

公开(公告)号：US08569116B2

公开(公告)日：2013-10-29

申请号：US13171228

申请日：2011-06-28

申请人： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

发明人： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

IPC分类号： H01L21/82 ,  H01L21/479 ,  H01L21/44

CPC分类号： H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

摘要翻译： 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。