Zero threshold voltage pFET and method of making same
    1.
    发明授权
    Zero threshold voltage pFET and method of making same 失效
    零阈值电压pFET及其制作方法

    公开(公告)号:US07005334B2

    公开(公告)日:2006-02-28

    申请号:US10845835

    申请日:2004-05-14

    IPC分类号: H01L21/336

    摘要: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

    摘要翻译: 零阈值电压(ZVt)pFET(104)及其制造方法。 ZVt pFET通过用逆向n阱(116)注入p型衬底(112),使得p型衬底材料的凹口(136)保持邻近衬底的表面而制成。 这是通过在对应于ZVt pFET的孔径(180)中具有口罩掩蔽区域(184)的n阱掩模(168)来实现的。 可以通过首先产生环形前体n阱(116')然后对衬底退火以使前体n阱的下部(140')的区域与 彼此隔开p型衬底材料的口袋。 在已经形成p型衬底材料的n阱和隔离袋之后,可以形成ZVt pFET的剩余结构,例如栅极绝缘体(128),栅极(132),源极(120)和漏极( 124)。

    Zero Threshold Voltage pFET and method of making same
    2.
    发明授权
    Zero Threshold Voltage pFET and method of making same 失效
    零阈值电压pFET及其制作方法

    公开(公告)号:US06825530B1

    公开(公告)日:2004-11-30

    申请号:US10250190

    申请日:2003-06-11

    IPC分类号: H01L2976

    摘要: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

    摘要翻译: 零阈值电压(ZVt)pFET(104)及其制造方法。 ZVt pFET通过用逆向n阱(116)注入p型衬底(112),使得p型衬底材料的凹口(136)保持邻近衬底的表面而制成。 这是通过在对应于ZVt pFET的孔径(180)中具有口罩掩蔽区域(184)的n阱掩模(168)来实现的。 可以通过首先产生环形前体n阱(116')然后对衬底退火以使前体n阱的下部(140')的区域与 彼此隔开p型衬底材料的口袋。 在已经形成p型衬底材料的n阱和隔离袋之后,可以形成ZVt pFET的剩余结构,例如栅极绝缘体(128),栅极(132),源极(120)和漏极( 124)。

    Isolated fully depleted silicon-on-insulator regions by selective etch
    3.
    发明授权
    Isolated fully depleted silicon-on-insulator regions by selective etch 失效
    通过选择性蚀刻隔离完全耗尽的绝缘体上硅区域

    公开(公告)号:US07190007B2

    公开(公告)日:2007-03-13

    申请号:US10710821

    申请日:2004-08-05

    IPC分类号: H01L29/47

    摘要: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

    摘要翻译: 本发明提供一种形成超薄且均匀的Si层的方法,包括以下步骤:提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽,其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。

    Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming
    4.
    发明授权
    Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
    需要单极编程的双极型二极管三维存储器的解码方案

    公开(公告)号:US08902690B2

    公开(公告)日:2014-12-02

    申请号:US13584423

    申请日:2012-08-13

    IPC分类号: G11C8/00

    摘要: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

    摘要翻译: 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法,包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态,并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

    Sense scheme for phase change material content addressable memory
    5.
    发明授权
    Sense scheme for phase change material content addressable memory 有权
    相变材料内容可寻址存储器的感应方案

    公开(公告)号:US08687398B2

    公开(公告)日:2014-04-01

    申请号:US13407813

    申请日:2012-02-29

    IPC分类号: G11C15/00

    CPC分类号: G11C15/00

    摘要: A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

    摘要翻译: 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间,将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时,发生评估阶段。

    Thermally insulated phase change material memory cells
    8.
    发明授权
    Thermally insulated phase change material memory cells 有权
    热绝缘相变材料存储单元

    公开(公告)号:US08536675B2

    公开(公告)日:2013-09-17

    申请号:US13364153

    申请日:2012-02-01

    IPC分类号: H01L23/52 H01L29/00

    摘要: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

    摘要翻译: 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中,相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中,孔隙电极形成在绝热层的孔隙和体积内,相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。

    Sub-lithographic printing method
    9.
    发明授权
    Sub-lithographic printing method 失效
    亚平版印刷法

    公开(公告)号:US08421194B2

    公开(公告)日:2013-04-16

    申请号:US13006403

    申请日:2011-01-13

    IPC分类号: H01L29/06

    CPC分类号: H01L21/0337

    摘要: A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.

    摘要翻译: 沟槽结构和集成电路,其包括衬底中的次光刻沟槽结构。 在一个实施例中,沟槽结构是通过用光刻掩膜形成一组沟槽而形成的,并且用一组间隔块块填充该组沟槽,该组间隔块包括彼此分离地可拆卸的两个交替间隔物材料。 在一个实施例中,形成的沟槽结构是光刻掩模的特征尺寸的厚度的十分之一。 沟槽结构的尺寸取决于用于形成一组步进间隔块的间隔材料层的厚度和数量。 间隔材料层的数量为n / 2,每个间隔材料层的厚度为光刻掩模的特征尺寸的十分之一。

    3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE
    10.
    发明申请
    3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE 有权
    使用双极性访问设备的双极存储器的3D架构

    公开(公告)号:US20130039110A1

    公开(公告)日:2013-02-14

    申请号:US13209405

    申请日:2011-08-14

    IPC分类号: G11C5/02 H01L21/02

    摘要: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.

    摘要翻译: 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外,在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件,其中在半导体晶片的一个层处制造多个存储器阵列,并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。