公开(公告)号：US20110189846A1

公开(公告)日：2011-08-04

申请号：US13020979

申请日：2011-02-04

申请人： Jeong Gil Lee ,  Chang-Won Lee ,  Sang-Woo Lee ,  Sun-Woo Lee ,  Ki-Hyun Hwang ,  Jae-Hwa Park ,  Eun-Ji Jung

发明人： Jeong Gil Lee ,  Chang-Won Lee ,  Sang-Woo Lee ,  Sun-Woo Lee ,  Ki-Hyun Hwang ,  Jae-Hwa Park ,  Eun-Ji Jung

IPC分类号： H01L21/28

CPC分类号： H01L21/28

摘要： A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.

摘要翻译： 公开了一种在半导体层上制造包括隧道氧化物层，初电电荷存储层和电介质层的非易失性存储器件的方法。 在介电层上形成第一多晶硅层。 在第一多晶硅层上形成阻挡层和第二多晶硅层。 对第二多晶硅层，势垒层，第一多晶硅层，电介质层，初电电荷存储层和隧道氧化物层进行图案化以形成隧道层图案，电荷存储层图案，介电层图案，第一 控制栅极图案，势垒层图案和第二多晶硅图案。 在第二多晶硅层上形成镍层。 对第二多晶硅图案和镍层进行热处理，以在阻挡层图案上形成包括NiSi的第二控制栅极图案。

公开(公告)号：US10026746B2

公开(公告)日：2018-07-17

申请号：US15604028

申请日：2017-05-24

申请人： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

发明人： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

IPC分类号： H01L27/115 ,  H01L27/1157 ,  H01L27/11524 ,  H01L23/535 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

公开(公告)号：US20180108664A1

公开(公告)日：2018-04-19

申请号：US15604028

申请日：2017-05-24

申请人： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

发明人： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

IPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L23/535 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC分类号： H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/788 ,  H01L29/792

摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.