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    Method of fabricating semiconductor device
    2.
    发明申请
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20100112772A1

    公开(公告)日：2010-05-06

    申请号：US12460945

    申请日：2009-07-27

    申请人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

    发明人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11573 ,  H01L21/28123 ,  H01L21/28282

    摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

    摘要翻译： 一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

    Gate Electrode of semiconductor device and method of forming the same
    3.
    发明申请
    Gate Electrode of semiconductor device and method of forming the same 审中-公开
    半导体器件的栅电极及其形成方法

    公开(公告)号：US20100105198A1

    公开(公告)日：2010-04-29

    申请号：US12458767

    申请日：2009-07-22

    申请人： Sang-woo Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    发明人： Sang-woo Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568

    摘要： A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode.

    摘要翻译： 形成半导体器件的栅电极的方法包括在衬底的外围电路区域中形成第一多晶硅层，在第一多晶硅层上形成阻挡层，阻挡层提供欧姆接触，形成包括 隧道绝缘层，电荷存储层和隔离绝缘层，在所述衬底的存储单元区域中，在所述阻挡层和所述阻挡绝缘层上形成第二多晶硅层，并且将所述第二多晶硅层硅化并形成硅化物栅极 电极。

    Method and apparatus for reducing digital to analog conversion (DAC) bits in frequency division multiple access (FDMA) system
    4.
    发明授权
    Method and apparatus for reducing digital to analog conversion (DAC) bits in frequency division multiple access (FDMA) system 失效
    用于减少频分多址（FDMA）系统中的数模转换（DAC）位的方法和装置

    公开(公告)号：US08493954B2

    公开(公告)日：2013-07-23

    申请号：US12337702

    申请日：2008-12-18

    申请人： Jun-Kyu Kang ,  In-Tae Kang ,  Jeong-Gil Lee ,  Bo-Rham Lee ,  Sang-Min Bae

    发明人： Jun-Kyu Kang ,  In-Tae Kang ,  Jeong-Gil Lee ,  Bo-Rham Lee ,  Sang-Min Bae

    IPC分类号： H04L27/08 ,  H04B7/208 ,  H04B1/44 ,  H04B7/204 ,  H04B1/04 ,  H04B1/06 ,  H04B7/00 ,  H01Q11/12

    CPC分类号： H04L27/2614 ,  H03M1/662 ,  H03M1/70 ,  H04L5/0044 ,  H04L27/2626

    摘要： A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.

    摘要翻译： 用于减少频分多址（FDMA）系统的发射机处的数模转换（DAC）比特的方法和装置减少了用于转换的比特数，以节省功率并降低操作成本。 该方法可以包括使用子载波分配信息，所需的信噪比（SNR）和峰均功率比（PAPR）来产生数字信号增益控制值和模拟信号增益控制值; 使用数字信号增益控制值控制输入到数模转换器的信号的增益; 使用数模转换器将受控增益的数字信号转换为模拟信号; 以及通过使用模拟信号增益控制值控制从数模转换器输出的信号的增益来恢复原始信号。

    Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes
    5.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes 有权
    形成具有堆叠栅电极的集成电路器件的方法

    公开(公告)号：US20090325371A1

    公开(公告)日：2009-12-31

    申请号：US12424922

    申请日：2009-04-16

    申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

    摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

    摘要翻译： 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

    Method for manufacturing a multiple walled capacitor of a semiconductor device
    8.
    发明授权
    Method for manufacturing a multiple walled capacitor of a semiconductor device 失效
    制造半导体器件的多层电容器的方法

    公开(公告)号：US5399518A

    公开(公告)日：1995-03-21

    申请号：US91369

    申请日：1993-07-15

    申请人： Sang-pil Sim ,  Joo-young Yun ,  Chang-kyu Hwang ,  Jeong-gil Lee ,  Chul-ho Shin ,  Won-woo Lee

    发明人： Sang-pil Sim ,  Joo-young Yun ,  Chang-kyu Hwang ,  Jeong-gil Lee ,  Chul-ho Shin ,  Won-woo Lee

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91 ,  H01L28/92

    摘要： A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known. Also, the storage electrode of the present invention has no sharp edges, so that leakage current can be minimized or avoided.

    摘要翻译： 一种用于制造半导体存储器件的电容器的双圆柱形存储电极的方法，利用用于形成外圆筒的外蚀刻掩模和用于形成内筒的内蚀刻掩模。 在半导体衬底上形成导电结构之后，在导电结构上形成用于形成外筒的外蚀刻掩模和用于形成内筒的内蚀刻掩模。 然后，使用外蚀刻掩模和内蚀刻掩模对导电结构进行各向异性蚀刻，从而形成双圆柱形第一电极。 由于可以从单个导电层获得双圆柱形存储电极，因此避免了天然氧化的影响。 此外，根据本发明的电容器的双圆柱形存储电极降低了结构碎裂的风险，因为电极是从一个材料层获得的，而不是如传统已知的层的组合。 此外，本发明的存储电极没有尖锐的边缘，使得可以最小化或避免泄漏电流。

    METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES
    10.
    发明申请
    METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
    制造非易失性存储器件的方法

    公开(公告)号：US20110189846A1

    公开(公告)日：2011-08-04

    申请号：US13020979

    申请日：2011-02-04

    申请人： Jeong Gil Lee ,  Chang-Won Lee ,  Sang-Woo Lee ,  Sun-Woo Lee ,  Ki-Hyun Hwang ,  Jae-Hwa Park ,  Eun-Ji Jung

    发明人： Jeong Gil Lee ,  Chang-Won Lee ,  Sang-Woo Lee ,  Sun-Woo Lee ,  Ki-Hyun Hwang ,  Jae-Hwa Park ,  Eun-Ji Jung

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28

    摘要： A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.

    摘要翻译： 公开了一种在半导体层上制造包括隧道氧化物层，初电电荷存储层和电介质层的非易失性存储器件的方法。 在介电层上形成第一多晶硅层。 在第一多晶硅层上形成阻挡层和第二多晶硅层。 对第二多晶硅层，势垒层，第一多晶硅层，电介质层，初电电荷存储层和隧道氧化物层进行图案化以形成隧道层图案，电荷存储层图案，介电层图案，第一 控制栅极图案，势垒层图案和第二多晶硅图案。 在第二多晶硅层上形成镍层。 对第二多晶硅图案和镍层进行热处理，以在阻挡层图案上形成包括NiSi的第二控制栅极图案。