公开(公告)号：US07989891B2

公开(公告)日：2011-08-02

申请号：US11755930

申请日：2007-05-31

申请人： Jianhong Zhu ,  Jinrong Zhou ,  David Wu ,  James F. Buller

发明人： Jianhong Zhu ,  Jinrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/7843

摘要： MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.

摘要翻译： 提供具有远程触点的MOS结构和用于制造这种MOS结构的方法。 在一个实施例中，一种用于制造MOS结构的方法包括提供半导体层，该半导体层至少部分地被隔离区包围，并且具有杂质掺杂的第一部分。 第一和第二MOS晶体管形成在第一部分内部和第一部分内。 晶体管基本上平行并且在它们之间限定了一个空间。 沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。 通过空间外部的绝缘材料形成触点，使得触点与晶体管电连通。

公开(公告)号：US08089125B2

公开(公告)日：2012-01-03

申请号：US11759454

申请日：2007-06-07

申请人： Jianhong Zhu ,  Ruigang Li ,  James F. Buller ,  David Wu

发明人： Jianhong Zhu ,  Ruigang Li ,  James F. Buller ,  David Wu

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/0617 ,  H01L27/0817 ,  H01L27/1203

摘要： An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.

摘要翻译： 集成电路系统包括集成电路，在集成电路附近形成三极管，并将连接器连接到三极管和集成电路。

公开(公告)号：US20080303089A1

公开(公告)日：2008-12-11

申请号：US11759454

申请日：2007-06-07

申请人： Jianhong Zhu ,  Ruigang Li ,  James F. Buller ,  David Wu

发明人： Jianhong Zhu ,  Ruigang Li ,  James F. Buller ,  David Wu

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/0617 ,  H01L27/0817 ,  H01L27/1203

摘要： An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.

摘要翻译： 集成电路系统包括集成电路，在集成电路附近形成三极管，并将连接器连接到三极管和集成电路。

公开(公告)号：US20110108949A1

公开(公告)日：2011-05-12

申请号：US12615796

申请日：2009-11-10

申请人： Jianhong Zhu ,  James F. Buller

发明人： Jianhong Zhu ,  James F. Buller

IPC分类号： H01L27/08 ,  H01L21/4763

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.

摘要翻译： 形成对电容器的两个节点具有良好导电性的金属电容器，并提高可靠性。 一个实施例包括交替的第一和第二金属线的第一层，交替的第三和第四金属线的第二层，第一和第二层之间的介电层，以及介电层中的通孔，将第一和第二金属线与 第三和第四金属线，其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段，第一宽度大于第二宽度，每个第一段邻近相邻的第二段的第二段 金属线，并且仅金属线的第一段与通孔重叠。 该设计使得能够保持金属线之间的间距，通孔与金属之间的间隔增加，并且通过两个网络的连接来保持，从而提高电容器的导电性和可靠性并保持电容密度。

公开(公告)号：US08357584B2

公开(公告)日：2013-01-22

申请号：US12615796

申请日：2009-11-10

申请人： Jianhong Zhu ,  James F. Buller

发明人： Jianhong Zhu ,  James F. Buller

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.

摘要翻译： 形成对电容器的两个节点具有良好导电性的金属电容器，并提高可靠性。 一个实施例包括交替的第一和第二金属线的第一层，交替的第三和第四金属线的第二层，第一和第二层之间的介电层，以及介电层中的通孔，将第一和第二金属线与 第三和第四金属线，其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段，第一宽度大于第二宽度，每个第一段邻近相邻的第二段的第二段 金属线，并且仅金属线的第一段与通孔重叠。 该设计使得能够保持金属线之间的间距，通孔与金属之间的间隔增加，并且通过两个网络的连接来保持，从而提高电容器的导电性和可靠性并保持电容密度。

公开(公告)号：US07670932B2

公开(公告)日：2010-03-02

申请号：US11762133

申请日：2007-06-13

申请人： Jianhong Zhu ,  Fred Hause ,  David Wu

发明人： Jianhong Zhu ,  Fred Hause ,  David Wu

IPC分类号： C12N15/75

CPC分类号： H01L21/28518 ,  H01L21/28247 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.

摘要翻译： 已经提供了具有用于较低接触电阻的接触突起的MOS结构以及用于制造这种MOS结构的方法。 在一个实施例中，一种方法包括提供半导体衬底，在衬底上制造栅极堆叠，以及在衬底上形成接触突起。 使用栅极堆叠作为离子注入掩模将电导率确定类型的离子注入到衬底内，以在衬底内形成杂质掺杂区域。 在接触突起上形成金属硅化物层，并且与金属硅化物层形成接触。 触点通过接触突起与杂质掺杂区电连通。

公开(公告)号：US07576357B1

公开(公告)日：2009-08-18

申请号：US11259572

申请日：2005-10-26

申请人： Jianhong Zhu ,  David Wu

发明人： Jianhong Zhu ,  David Wu

IPC分类号： H01L23/58

CPC分类号： H01L22/14 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of detecting damage to at least one dielectric layer in an IC die by determining a capacitance factor. The capacitance factor can be used to determine damage in a low-k dielectric material. A system for detecting damage can include a conductive line structure for measuring capacitance and software or a device for determining the capacitance to determine the damage.

摘要翻译： 一种通过确定电容因子来检测IC芯片中的至少一个电介质层的损伤的方法。 电容因数可用于确定低k电介质材料的损伤。 用于检测损伤的系统可以包括用于测量电容和软件的导线结构或用于确定电容以确定损坏的装置。

公开(公告)号：US07271047B1

公开(公告)日：2007-09-18

申请号：US11327641

申请日：2006-01-06

申请人： Jianhong Zhu ,  Mark Michael ,  David Wu

发明人： Jianhong Zhu ,  Mark Michael ,  David Wu

IPC分类号： H01L21/8238

CPC分类号： H01L22/34 ,  H01L22/14

摘要： A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

摘要翻译： 提供了测试结构及其使用和制造方法。 在一个方面，提供一种测试结构，其包括具有第一端和第二导体的第一导体，第二导​​体具有位于第一端上方的第二端。 第三导体位于第一导体的第一端和第二导体的第二端之间。 第一电极以距离第三导体第一距离的第一导体耦合到第一导体，第二电极以距离第三导体第二距离的方式耦合到第一导体。 第三电极以距离第三导体第三距离的方式耦合到第二导体，并且第四电极在距离第三导体的第四距离处耦合到第二导体。 第一至第四电极提供电压检测抽头，并且第一和第二导体提供电流检测抽头，从该第三导体提供第三导体的电阻。

公开(公告)号：US20060024849A1

公开(公告)日：2006-02-02

申请号：US10902578

申请日：2004-07-30

申请人： Jianhong Zhu ,  Dorel Toma

发明人： Jianhong Zhu ,  Dorel Toma

IPC分类号： H01L21/00

CPC分类号： H01L21/31695 ,  G01N7/14 ,  G01N15/088 ,  G01N2015/086 ,  G01N2021/3595 ,  H01L21/02126 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/0234 ,  H01L21/02343 ,  H01L22/12

摘要： A method and system for diagnosing the effectiveness of a treatment on a porous material. For example, the porous material can include a porous low dielectric constant material. In particular, the method can utilize FTIR spectroscopy to characterize the porosity of materials, and assess the effectiveness of sealing pores in the material.

摘要翻译： 用于诊断多孔材料处理有效性的方法和系统。 例如，多孔材料可以包括多孔低介电常数材料。 特别地，该方法可以利用FTIR光谱来表征材料的孔隙度，并评估材料中密封孔的有效性。

公开(公告)号：US07553769B2

公开(公告)日：2009-06-30

申请号：US10682196

申请日：2003-10-10

申请人： Dorel Ioan Toma ,  Jianhong Zhu ,  Kazuhiro Hamamoto

发明人： Dorel Ioan Toma ,  Jianhong Zhu ,  Kazuhiro Hamamoto

IPC分类号： H01L21/302

CPC分类号： H01L21/02337 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to a CxHy containing material, wherein x and y are each integers greater than or equal to a value of unity. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue. Moreover, preparation for barrier layer and metallization of features in the film may include treating by performing sealing of sidewall surfaces of the feature to close exposed pores and provide a surface for barrier film deposition.

摘要翻译： 用于处理电介质膜的方法和系统包括将电介质膜的至少一个表面暴露于含CxHy的材料，其中x和y各自为大于或等于一个值的整数。 介电膜可以包括具有或不具有在干蚀刻处理之后形成的蚀刻特征的孔的低介电常数膜。 作为蚀刻处理或灰化的结果，形成在电介质膜中的特征中的暴露表面可能被损坏或激活，导致污染物的保留，水分的吸收，介电常数的增加等。损坏的表面，例如这些 通过执行愈合这些表面中的至少一个来处理，例如恢复介电常数（即，降低介电常数）并清洁这些表面以去除污染物，水分或残留物。 此外，膜的特征的阻挡层和金属化的制备可以包括通过执行特征的侧壁表面的密封来封闭暴露的孔并提供用于阻挡膜沉积的表面来进行处理。