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    PROCESS FOR SELECTIVE GROWTH OF FILMS DURING ECP PLATING
    1.
    发明申请
    PROCESS FOR SELECTIVE GROWTH OF FILMS DURING ECP PLATING 失效
    ECP镀层选择生长膜的工艺

    公开(公告)号：US20090215264A1

    公开(公告)日：2009-08-27

    申请号：US12037578

    申请日：2008-02-26

    申请人： Jick M. Yu ,  Wei D. Wang ,  Rongjun Wang ,  Hua Chung

    发明人： Jick M. Yu ,  Wei D. Wang ,  Rongjun Wang ,  Hua Chung

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76879 ,  C25D5/02 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76873

    摘要： Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.

    摘要翻译： 提供了在电镀工艺中控制金属在基片的场区上沉积的方法。 在一个方面，电介质层在等离子体上沉积在图案化衬底的场区上，留下在开口中暴露的导电表面。 场区域上的电镀被减少或消除，导致无空隙特征和最小的多余电镀。 在另一方面，可以使用可以是金属的电阻层来代替电介质。 在另一方面，导电场区域的表面被修改以相对于开口的侧壁和底部改变其化学势。

    Process for selective growth of films during ECP plating
    2.
    发明授权
    Process for selective growth of films during ECP plating 失效
    ECP电镀过程中膜的选择性生长

    公开(公告)号：US08119525B2

    公开(公告)日：2012-02-21

    申请号：US12037578

    申请日：2008-02-26

    申请人： Jick M. Yu ,  Wei D. Wang ,  Rongjun Wang ,  Hua Chung

    发明人： Jick M. Yu ,  Wei D. Wang ,  Rongjun Wang ,  Hua Chung

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76879 ,  C25D5/02 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76873

    摘要： Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.

    摘要翻译： 提供了在电镀工艺中控制金属在基片的场区上沉积的方法。 在一个方面，电介质层在等离子体上沉积在图案化衬底的场区上，留下在开口中暴露的导电表面。 场区域上的电镀被减少或消除，导致无空隙特征和最小的多余电镀。 在另一方面，可以使用可以是金属的电阻层来代替电介质。 在另一方面，导电场区域的表面被修改以相对于开口的侧壁和底部改变其化学势。

    Partially filling copper seed layer
    3.
    发明授权
    Partially filling copper seed layer 有权
    部分填充铜籽层

    公开(公告)号：US06899796B2

    公开(公告)日：2005-05-31

    申请号：US10428476

    申请日：2003-05-01

    申请人： Wei D. Wang ,  Anantha K. Subramani ,  Jianming Fu ,  Praburam Gopalraja ,  Jick M. Yu ,  Fusen Chen

    发明人： Wei D. Wang ,  Anantha K. Subramani ,  Jianming Fu ,  Praburam Gopalraja ,  Jick M. Yu ,  Fusen Chen

    IPC分类号： C23C14/04 ,  C23C14/34 ,  C23C14/54 ,  H01L21/285 ,  H01L21/768 ,  B05D1/36

    CPC分类号： C23C14/046 ,  C23C14/185 ,  C23C14/345 ,  C23C14/3492 ,  C23C14/541 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877

    摘要： A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.

    摘要翻译： 将铜填充到高纵横比或双镶嵌结构的两步法。 第一步在不超过100℃的低温下进行喷射，并且至少部分高晶片偏置，从而填充孔的下半部分。 初始铜溅射优选通过多个低水平和高水平基座偏压的周期进行，以在暴露的拐角上沉积铜，并且在沉积在孔中深处时从角部溅射所得到的突出端。 第二步可以包括在较高温度例如至少200℃进行的电化学电镀或溅射，并且具有较低的晶片偏置以完成孔填充。 在本发明的另一方面，将扩散促进气体如氢气加入到铜溅射等离子体中。

    Diffusion enhanced ion plating for copper fill
    4.
    发明授权
    Diffusion enhanced ion plating for copper fill 失效
    扩散增强离子电镀铜填充

    公开(公告)号：US06884329B2

    公开(公告)日：2005-04-26

    申请号：US10340564

    申请日：2003-01-10

    申请人： Wei D. Wang ,  Anantha K. Subramani ,  Jianming Fu ,  Praburam Gopalraja ,  Jick M. Yu ,  Fusen Chen

    发明人： Wei D. Wang ,  Anantha K. Subramani ,  Jianming Fu ,  Praburam Gopalraja ,  Jick M. Yu ,  Fusen Chen

    IPC分类号： C23C14/04 ,  C23C14/34 ,  C23C14/54 ,  H01L21/285 ,  H01L21/768

    CPC分类号： H01L21/76844 ,  C23C14/046 ,  C23C14/345 ,  C23C14/541 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76877

    摘要： A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.

    摘要翻译： 一种通过等离子体溅射工艺将铜填充到高纵横比通孔并允许消除电化学电镀的方法。 在本发明的一个方面，溅射被分为在不超过100℃的低温下进行的第一步骤和至少部分高晶片偏压，从而填充孔的下半部分，并且第二步骤 步骤在较高的温度例如至少200℃进行，并且至少部分低晶片偏置以完成孔填充。 在本发明的另一方面，将扩散促进气体如氢气加入到铜溅射等离子体中。 在另一方面，即使在最终填充阶段，铜溅射也是通过多个低级和高级底座偏压循环进行的，以便在暴露的拐角上沉积铜并从拐角溅射。

    Shutdown path performance test for permanent magnet AC motor in hybrid powertrain
    8.
    发明授权
    Shutdown path performance test for permanent magnet AC motor in hybrid powertrain 有权
    混合动力总成中永磁交流电机的停机路径性能试验

    公开(公告)号：US08013554B2

    公开(公告)日：2011-09-06

    申请号：US12240378

    申请日：2008-09-29

    申请人： Stephen T. West ,  Wei D. Wang

    发明人： Stephen T. West ,  Wei D. Wang

    IPC分类号： H02P7/00

    CPC分类号： B60W20/50 ,  B60K6/44 ,  B60W10/06 ,  B60W10/08 ,  B60W10/26 ,  B60W20/00 ,  Y02T10/623 ,  Y02T10/6286 ,  Y02T10/7258

    摘要： A diagnostic system for a hybrid vehicle comprises a motor control module and a fault diagnostic module. The motor control module controls torque output of an electric motor having a predetermined number of phases. The fault diagnostic module determines a position of a rotor of the electric motor, aligns the rotor with a phase angle of one of the phases, selectively diagnoses a fault based on a current of at least one of the phases, and selectively disables the electric motor based on the diagnosis.

    摘要翻译： 一种用于混合动力车辆的诊断系统包括马达控制模块和故障诊断模块。 电动机控制模块控制具有预定数量相位的电动机的转矩输出。 故障诊断模块确定电动机的转子的位置，使转子与其中一相的相位角对准，基于至少一相的电流选择性地诊断故障，并选择性地禁用电动机 基于诊断。

    METHOD AND CIRCUIT FOR PROCESSING A RESOLVER FAULT
    9.
    发明申请
    METHOD AND CIRCUIT FOR PROCESSING A RESOLVER FAULT 有权
    用于处理解决方案故障的方法和电路

    公开(公告)号：US20110043145A1

    公开(公告)日：2011-02-24

    申请号：US12543708

    申请日：2009-08-19

    申请人： Wei D. Wang ,  Bon Ho Bae ,  Stephen T. West ,  Rick H. Schroeder

    发明人： Wei D. Wang ,  Bon Ho Bae ,  Stephen T. West ,  Rick H. Schroeder

    IPC分类号： H02P6/16

    CPC分类号： G01D5/24476

    摘要： A method of processing a resolver fault in a motor generator unit (MGU) includes receiving a position signal from a resolver describing a measured angular position of a rotor of the MGU, determining the presence of the resolver fault using the position signal, and calculating or extrapolating an estimated rotor position when the resolver fault is determined. A predetermined resolver fault state may be determined using a measured duration of the resolver fault, and the MGU may be controlled using the estimated rotor position for at least a portion of the duration of the resolver fault. A motor control circuit is operable for processing the resolver fault using the above method, and may automatically vary a torque output or a pulse-width modulation (PWM) of the MGU depending on the duration of the resolver fault.

    摘要翻译： 一种处理电动发电机单元（MGU）中的解算器故障的方法包括从解析器接收描述MGU的转子的测量角位置的位置信号，使用位置信号确定解析器故障的存在，以及计算或 当确定旋转变压器故障时，外推估计的转子位置。 可以使用解析器故障的测量持续时间来确定预定的解算器故障状态，并且可以使用估计的转子位置来控制解调器故障持续时间的至少一部分的MGU。 电动机控制电路可操作以使用上述方法处理旋转变压器故障，并且可以根据解算器故障的持续时间自动地改变MGU的转矩输出或脉冲宽度调制（PWM）。

    Krypton sputtering of thin tungsten layer for integrated circuits
    10.
    发明授权
    Krypton sputtering of thin tungsten layer for integrated circuits 有权
    用于集成电路的薄钨层的氪溅射

    公开(公告)号：US07790604B2

    公开(公告)日：2010-09-07

    申请号：US11841205

    申请日：2007-08-20

    申请人： Wei D. Wang ,  Srinivas Gandikota ,  Kishore Lavu

    发明人： Wei D. Wang ,  Srinivas Gandikota ,  Kishore Lavu

    IPC分类号： H01L21/00

    CPC分类号： C23C14/16 ,  C23C14/0641 ,  H01L21/28061 ,  H01L29/4941

    摘要： A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

    摘要翻译： 通过等离子体溅射工艺在钨沉积中使用氪作为溅射工作气体的钨沉积钨层的方法。 在氮化钨的反应溅射沉积期间，可以使用氩作为溅射工作气体。 当钨层的厚度小于50nm时，降低钨电阻率的有益效果增加，当小于35nm时，钨电阻率的降低进一步增加。 该方法可以用于在MOS晶体管的硅栅极区域上的栅极氧化物层上形成包括多晶硅层的栅极堆叠，其中氮化钨作为势垒。 可以实施本发明的等离子体溅射室包括氪气，氩气和氮气的气源。