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    Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers
    1.
    发明授权
    Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers 有权
    在两个氧气密封层之间具有含氧层的场效应晶体管的间隔结构

    公开(公告)号：US08450834B2

    公开(公告)日：2013-05-28

    申请号：US12706191

    申请日：2010-02-16

    申请人： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

    发明人： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/401 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

    摘要： This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.

    摘要翻译： 本公开涉及场效应晶体管的间隔结构。 场效应晶体管的示例性结构包括：衬底; 栅极结构，其具有覆盖所述衬底的侧壁; 所述栅极结构的一侧上的所述衬底中的硅化物区域具有最靠近所述栅极结构的内部边缘; 与栅极结构的侧壁相邻的第一氧气密封层; 邻接所述侧壁上的所述第一氧气密封层并且还包括在所述衬底上延伸的部分的含氧层; 以及邻接所述含氧层并在所述基底上的所述含氧层的所述部分上延伸的第二氧气密封层，其中所述第二氧气密封层的外边缘从所述硅化物区域的内边缘偏移。

    Method for main spacer trim-back
    4.
    发明授权
    Method for main spacer trim-back 有权
    主间隔装饰方法

    公开(公告)号：US08343867B2

    公开(公告)日：2013-01-01

    申请号：US13234674

    申请日：2011-09-16

    申请人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    发明人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

    摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

    摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。

    Method and device with gate structure formed over the recessed top portion of the isolation structure
    5.
    发明授权
    Method and device with gate structure formed over the recessed top portion of the isolation structure 有权
    具有栅极结构的方法和装置形成在隔离结构的凹入的顶部上

    公开(公告)号：US08329521B2

    公开(公告)日：2012-12-11

    申请号：US12830107

    申请日：2010-07-02

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    IPC分类号： H01L21/8238 ,  H01L27/148

    CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

    摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

    摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

    Main spacer trim-back method for replacement gate process
    6.
    发明授权
    Main spacer trim-back method for replacement gate process 有权
    替代浇口工艺的主要间隔件修剪方法

    公开(公告)号：US08039388B1

    公开(公告)日：2011-10-18

    申请号：US12730375

    申请日：2010-03-24

    申请人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    发明人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

    摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

    摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。

    METHOD AND APPARATUS FOR IMPROVING GATE CONTACT
    7.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING GATE CONTACT 有权
    改善门接触的方法和装置

    公开(公告)号：US20120001259A1

    公开(公告)日：2012-01-05

    申请号：US12830107

    申请日：2010-07-02

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

    摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

    摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

    Semiconductor device having a SiGe feature and a metal gate stack
    10.
    发明授权
    Semiconductor device having a SiGe feature and a metal gate stack 有权
    具有SiGe特征的半导体器件和金属栅极堆叠

    公开(公告)号：US08373199B2

    公开(公告)日：2013-02-12

    申请号：US13194332

    申请日：2011-07-29

    申请人： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hua Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

    发明人： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hua Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

    IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

    摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。