公开(公告)号：US09000533B2

公开(公告)日：2015-04-07

申请号：US13457079

申请日：2012-04-26

申请人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/51

CPC分类号： H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US08343867B2

公开(公告)日：2013-01-01

申请号：US13234674

申请日：2011-09-16

申请人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。

公开(公告)号：US08450834B2

公开(公告)日：2013-05-28

申请号：US12706191

申请日：2010-02-16

申请人： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

发明人： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/401 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.

摘要翻译： 本公开涉及场效应晶体管的间隔结构。 场效应晶体管的示例性结构包括：衬底; 栅极结构，其具有覆盖所述衬底的侧壁; 所述栅极结构的一侧上的所述衬底中的硅化物区域具有最靠近所述栅极结构的内部边缘; 与栅极结构的侧壁相邻的第一氧气密封层; 邻接所述侧壁上的所述第一氧气密封层并且还包括在所述衬底上延伸的部分的含氧层; 以及邻接所述含氧层并在所述基底上的所述含氧层的所述部分上延伸的第二氧气密封层，其中所述第二氧气密封层的外边缘从所述硅化物区域的内边缘偏移。

公开(公告)号：US20110198675A1

公开(公告)日：2011-08-18

申请号：US12706191

申请日：2010-02-16

申请人： Jin-Aun NG ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

发明人： Jin-Aun NG ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

IPC分类号： H01L29/78 ,  H01L21/311

CPC分类号： H01L29/401 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.

摘要翻译： 本公开涉及场效应晶体管的间隔结构。 场效应晶体管的示例性结构包括：衬底; 栅极结构，其具有覆盖所述衬底的侧壁; 所述栅极结构的一侧上的所述衬底中的硅化物区域具有最靠近所述栅极结构的内部边缘; 与栅极结构的侧壁相邻的第一氧气密封层; 邻接所述侧壁上的所述第一氧气密封层并且还包括在所述衬底上延伸的部分的含氧层; 以及邻接所述含氧层并在所述基底上的所述含氧层的所述部分上延伸的第二氧气密封层，其中所述第二氧气密封层的外边缘从所述硅化物区域的内边缘偏移。

公开(公告)号：US08039388B1

公开(公告)日：2011-10-18

申请号：US12730375

申请日：2010-03-24

申请人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。

公开(公告)号：US08587074B2

公开(公告)日：2013-11-19

申请号：US13101727

申请日：2011-05-05

申请人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed.

摘要翻译： 一种器件包括漏极，源极和栅极叠层。 栅极堆叠具有栅极电介质层，立即在栅极电介质层的顶部上的栅极导电层，以及立即在栅极导电层顶部上的第一栅极和第二栅极层。 第一栅极层具有比第二栅极层的第二电阻高的第一电阻。 第二栅极层是导电的，与栅极导电层电耦合，并且具有被配置为用作器件的栅极接触端子的接触端子。 还公开了栅极堆叠的制造方法。

公开(公告)号：US09142414B2

公开(公告)日：2015-09-22

申请号：US13331214

申请日：2011-12-20

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

摘要翻译： 一种方法包括形成PMOS器件。 该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理 使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。 第二含金属层具有低于硅的中间间隙功函数的功函数。 第一含金属层和第二含金属层形成PMOS器件的栅极。

公开(公告)号：US20130154022A1

公开(公告)日：2013-06-20

申请号：US13331214

申请日：2011-12-20

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

摘要翻译： 一种方法包括形成PMOS器件。 该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理 使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。 第二含金属层具有低于硅的中间间隙功函数的功函数。 第一含金属层和第二含金属层形成PMOS器件的栅极。

公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

申请人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

发明人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC分类号： H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US09070623B2

公开(公告)日：2015-06-30

申请号：US12897559

申请日：2010-10-04

申请人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Kuei Shun Chen ,  Cheng Cheng Kuo ,  George Liu ,  Tsung-Chieh Tsai ,  Yuhi-Jier Mii

发明人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Kuei Shun Chen ,  Cheng Cheng Kuo ,  George Liu ,  Tsung-Chieh Tsai ,  Yuhi-Jier Mii

IPC分类号： H01L21/338 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7831

摘要： Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.

摘要翻译： 公开了形成半导体结构和半导体结构的方法。 在一个实施例中，一种方法包括在衬底上形成栅极电介质层，在栅极电介质层上形成栅极电极层，并蚀刻栅极电极层和栅极电介质层以形成水平栅极结构和垂直栅极结构， 其中所述水平栅极结构和所述垂直栅极结构通过互连部分连接。 该方法还包括形成覆盖水平栅极结构和垂直栅极结构的光致抗蚀剂，其中光致抗蚀剂具有暴露水平栅极结构和垂直栅极结构之间的互连部分的间隙，然后蚀刻互连部分。