Maintaining packet sequence using cell flow control
    1.
    发明申请
    Maintaining packet sequence using cell flow control 有权
    使用单元流控制维护分组序列

    公开(公告)号:US20050201400A1

    公开(公告)日:2005-09-15

    申请号:US11004260

    申请日:2004-12-03

    IPC分类号: H04L12/28 H04L12/43 H04L12/56

    CPC分类号: H04L47/624 H04L47/6225

    摘要: Packets out-of-sequence problem can be solved by using a window flow control scheme that can dispatch traffic at the cell level, in a round robin fashion, as evenly as possible. Each VOQ at the input port has a sequence head pointer that is used to assign sequence numbers (SN) to the cells. Also a sequence tail pointer is available at each VOQ that is used to acknowledge and limit the amount of cells that can be sent to the output ports based on the window size of the scheme. Each VIQ at the output port has a sequence pointer or sequence number (SN) pointer that indicates to the VIQ which cell to wait for. Once the VIQ receives the cell that the SN pointer indicated, the output port sends an ACK packet back to the input port. By using sequence numbers and the relevant pointers, the packet out-of-sequence problem is solved.

    摘要翻译: 可以通过使用可以尽可能均匀地以循环方式在小区级分配流量的窗口流控制方案来解决分组排序问题。 输入端口的每个VOQ都有一个序列头指针,用于向单元格分配序列号(SN)。 每个VOQ也可以使用一个序列尾部指针,用于根据该方案的窗口大小来确认和限制可以发送到输出端口的单元的数量。 输出端口上的每个VIQ都有一个序列指针或序列号(SN)指针,指示VIQ要等待哪个单元。 一旦VIQ接收到SN指针指示的单元,输出端口将ACK包发送回输入端口。 通过使用序列号和相关指针,解决了数据包失序问题。

    Switch module memory structure and per-destination queue flow control for use in a switch
    2.
    发明申请
    Switch module memory structure and per-destination queue flow control for use in a switch 有权
    切换模块存储器结构和每个目标队列流控制,用于交换机

    公开(公告)号:US20050002410A1

    公开(公告)日:2005-01-06

    申请号:US10776575

    申请日:2004-02-11

    IPC分类号: H04L12/28

    CPC分类号: H04L49/1523 H04L49/506

    摘要: To use the memory space more effectively, cell memory can be shared by an input link and all output links. To prevent one flow from occupying the entire memory space, a threshold may be provided for the queue. The queue threshold may accommodate the RTT delay of the link. Queue length information about a downstream switch module may be sent to an upstream switch module via cell headers in every credit update period per link. Cell and/or credit loss may be recovered from. Increasing the credit update period reduces the cell header bandwidth but doesn't degrade performance significantly. Sending a credit per link simplifies implementation and eliminates interference between other links.

    摘要翻译: 为了更有效地使用存储器空间,单元存储器可以由输入链路和所有输出链路共享。 为了防止一个流占用整个存储器空间,可以为队列提供阈值。 队列阈值可以适应链路的RTT延迟。 关于下游交换机模块的队列长度信息可以在每个链路的每个信用更新周期中通过小区头发送到上游交换机模块。 可以从中回收信元和/或信用损失。 增加信用更新周期会降低单元头带宽,但不会显着降低性能。 每个链接发送信用简化了实现,消除了其他链接之间的干扰。

    Packet-level multicasting
    3.
    发明申请
    Packet-level multicasting 有权
    数据包级多播

    公开(公告)号:US20050025171A1

    公开(公告)日:2005-02-03

    申请号:US10872187

    申请日:2004-06-18

    IPC分类号: H04L12/56

    CPC分类号: H04L49/10

    摘要: Packet-level multicasting may be used to avoid the cell header and the memory size problems. One or more multicast control cells may be appended before one or more data cells of a multicast packet to carry multicast bitmap information. The control cell may be stored at the cell memory. This approach is suitable for a multi-plane, multi-stage packet switch.

    摘要翻译: 可以使用分组级多播来避免单元头和存储器大小问题。 可以在多播分组的一个或多个数据单元之前附加一个或多个多播控制单元以携带多播位图信息。 控制单元可以存储在单元存储器中。 该方法适用于多平面多级分组交换机。

    Packet reassembly and deadlock avoidance for use in a packet switch
    4.
    发明申请
    Packet reassembly and deadlock avoidance for use in a packet switch 有权
    分组重组和死锁避免用于分组交换机

    公开(公告)号:US20050025141A1

    公开(公告)日:2005-02-03

    申请号:US10872332

    申请日:2004-06-18

    IPC分类号: H04L12/28

    CPC分类号: H04L49/1523 H04L49/552

    摘要: Practical packet reassembly in large, multi-plane, multi-stage switches is possible by using a scheduling technique called dynamic packet interleaving. With dynamic packet interleaving scheduling, if more than one packet is contending for the same output link in a switch module, an arbiter in the switch module gives priority to a partial packet (i.e., to a packet that has had at least one cell sent to the queue). The number of reassembly queues required to ensure reassembly is dramatically reduced (e.g., to the number of paths multiplied by the number of scheduling priorities). Deadlock may be avoided by guaranteeing (e.g., reserving) at least one cell space for all partial packets.

    摘要翻译: 通过使用称为动态分组交织的调度技术,可以在大型多平面多级交换机中实际的分组重组。 通过动态分组交织调度,如果交换机模块中的多个分组正在竞争相同的输出链路,交换机模块中的仲裁器将优先考虑部分分组(即,至少有一个小区被发送到 队列)。 确保重新组装所需的重组队列的数量大大减少(例如,到路由数量乘以调度优先级的数量)。 可以通过为所有部分分组保证(例如,保留)至少一个小区空间来避免死锁。

    Apparatus for driving motor of electric vehicle
    5.
    发明授权
    Apparatus for driving motor of electric vehicle 有权
    用于驱动电动汽车电机的装置

    公开(公告)号:US08558492B2

    公开(公告)日:2013-10-15

    申请号:US12943640

    申请日:2010-11-10

    IPC分类号: H02H7/08

    摘要: An apparatus for driving a motor of an electric vehicle is provided. The apparatus includes a capacitor supplied with power by a battery; an inverter configured to include a plurality of switching elements, convert direct current (DC) power stored in the capacitor into alternating current (AC) power in accordance with the switching of the switching elements and drive a motor with the AC power; and a capacitor protector provided between the battery and the capacitor and configured to consume initial power supplied by the battery at an early stage of the supply of power by the battery, the capacitor protector including a common resistor that consumes the DC power stored in the capacitor when the capacitor is discharged. Therefore, it is possible to guarantee the reliability of the apparatus.

    摘要翻译: 提供一种用于驱动电动车辆的电动机的装置。 该装置包括由电池供电的电容器; 逆变器,被配置为包括多个开关元件,根据开关元件的切换将电容器中存储的直流电(DC)功率转换为交流(AC)电力,并用交流电驱动电动机; 以及电容器保护器,其设置在电池和电容器之间并且被配置为在电池供电的早期消耗由电池提供的初始功率,电容器保护器包括消耗存储在电容器中的直流电力的公共电阻器 当电容器放电时。 因此,可以保证设备的可靠性。

    Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch
    6.
    发明申请
    Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch 有权
    带有负载平衡的数据包序列维护,交换机中的线路头阻塞避免

    公开(公告)号:US20050002334A1

    公开(公告)日:2005-01-06

    申请号:US10776574

    申请日:2004-02-11

    IPC分类号: H04L1/00 H04L12/56

    摘要: To avoid packet out-of-sequence problems, while providing good load balancing, each input port of a switch monitors the outstanding number of packets for each flow group. If there is an outstanding packet in the switch fabric, the following packets of the same flow group should follow the same path. If there is no outstanding packet of the same flow group in the switch fabric, the (first, and therefore subsequent) packets of the flow can choose a less congested path to improve load balancing performance without causing an out-of-sequence problem. To avoid HOL blocking without requiring too many queues, an input module may include two stages of buffers. The first buffer stage may be a virtual output queue (VOQ) and second buffer stage may be a virtual path queue (VPQ). At the first stage, the packets may be stored at the VOQs, and the HOL packet of each VOQ may be sent to the VPQ. By allowing each VOQ to send at most one packet to VPQ, HOL blocking can be mitigated dramatically.

    摘要翻译: 为了避免数据包失序问题,在提供良好的负载均衡的情况下,交换机的每个输入端口都会监视每个流组的未知数量。 如果交换机结构中存在未完成的报文,则同一流程组的以下报文应遵循相同的路径。 如果交换机结构中没有相同流组的未完成报文,则流的(第一个,后续的)报文可以选择较少拥塞的路径,以提高负载均衡性能,而不会导致失序问题。 为了避免HOL阻塞而不需要太多的队列,输入模块可以包括两级缓冲器。 第一缓冲级可以是虚拟输出队列(VOQ),第二缓冲级可以是虚拟路径队列(VPQ)。 在第一阶段,分组可以存储在VOQ中,并且每个VOQ的HOL分组可以被发送到VPQ。 通过允许每个VOQ最多发送一个数据包到VPQ,HOL阻塞可以大大减轻。

    Power module and vehicle having the same
    7.
    发明授权
    Power module and vehicle having the same 有权
    电源模块和车辆具有相同的功能

    公开(公告)号:US08598733B2

    公开(公告)日:2013-12-03

    申请号:US12945433

    申请日:2010-11-12

    IPC分类号: B60L1/00

    CPC分类号: H02K11/33

    摘要: Provided is a power module in which a motor and a motor driving unit are efficiently configured and a vehicle having the same. The power module includes a power module case forming an external form; an inverter provided within the power module case and configured to convert a direct current (DC) power into an alternating current (AC) power; an AC power conductor provided in the power module case and connected to the inverter to cause the AC power converted by the inverter to flow therethrough; and a motor provided in the power module case and connected to the AC power conductor to receive the AC power and generate a rotational force.

    摘要翻译: 具有电动机和电动机驱动单元被有效地构成的电力模块和具有该电力模块的车辆。 电源模块包括形成外部形式的电源模块外壳; 设置在功率模块壳体内并被配置为将直流(DC)功率转换成交流(AC)功率的逆变器; 设置在所述电源模块壳体内并连接到所述逆变器以使由所述逆变器转换的交流电力流过其中的交流电力导体; 以及电动机,设置在所述电源模块壳体中并连接到所述AC电力导体以接收所述AC电力并产生旋转力。

    POWER MODULE AND VEHICLE HAVING THE SAME
    9.
    发明申请
    POWER MODULE AND VEHICLE HAVING THE SAME 有权
    功率模块和具有相同功能的车辆

    公开(公告)号:US20110114397A1

    公开(公告)日:2011-05-19

    申请号:US12945433

    申请日:2010-11-12

    IPC分类号: B60L11/18 H02K5/22

    CPC分类号: H02K11/33

    摘要: Provided is a power module in which a motor and a motor driving unit are efficiently configured and a vehicle having the same. The power module includes a power module case forming an external form; an inverter provided within the power module case and configured to convert a direct current (DC) power into an alternating current (AC) power; an AC power conductor provided in the power module case and connected to the inverter to cause the AC power converted by the inverter to flow therethrough; and a motor provided in the power module case and connected to the AC power conductor to receive the AC power and generate a rotational force.

    摘要翻译: 具有电动机和电动机驱动单元被有效地构成的电力模块和具有该电力模块的车辆。 电源模块包括形成外部形式的电源模块外壳; 设置在功率模块壳体内并被配置为将直流(DC)功率转换成交流(AC)功率的逆变器; 设置在所述电源模块壳体内并连接到所述逆变器以使由所述逆变器转换的交流电力流过其中的交流电力导体; 以及电动机,设置在所述电源模块壳体中并连接到所述AC电力导体以接收所述AC电力并产生旋转力。

    Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch
    10.
    发明授权
    Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch 有权
    带有负载平衡的数据包序列维护,交换机中的线路头阻塞避免

    公开(公告)号:US07894343B2

    公开(公告)日:2011-02-22

    申请号:US10776574

    申请日:2004-02-11

    IPC分类号: G01R31/08

    摘要: To avoid packet out-of-sequence problems, while providing good load balancing, each input port of a switch monitors the outstanding number of packets for each flow group. If there is an outstanding packet in the switch fabric, the following packets of the same flow group should follow the same path. If there is no outstanding packet of the same flow group in the switch fabric, the (first, and therefore subsequent) packets of the flow can choose a less congested path to improve load balancing performance without causing an out-of-sequence problem. To avoid HOL blocking without requiring too many queues, an input module may include two stages of buffers. The first buffer stage may be a virtual output queue (VOQ) and second buffer stage may be a virtual path queue (VPQ). At the first stage, the packets may be stored at the VOQs, and the HOL packet of each VOQ may be sent to the VPQ. By allowing each VOQ to send at most one packet to VPQ, HOL blocking can be mitigated dramatically.

    摘要翻译: 为了避免数据包失序问题,在提供良好的负载均衡的情况下,交换机的每个输入端口都会监视每个流组的未知数量。 如果交换机结构中存在未完成的报文,则同一流程组的以下报文应遵循相同的路径。 如果交换机结构中没有相同流组的未完成报文,则流的(第一个,后续的)报文可以选择较少拥塞的路径,以提高负载均衡性能,而不会导致失序问题。 为了避免HOL阻塞而不需要太多的队列,输入模块可以包括两级缓冲器。 第一缓冲级可以是虚拟输出队列(VOQ),第二缓冲级可以是虚拟路径队列(VPQ)。 在第一阶段,分组可以存储在VOQ中,并且每个VOQ的HOL分组可以被发送到VPQ。 通过允许每个VOQ最多发送一个数据包到VPQ,HOL阻塞可以大大减轻。