公开(公告)号：US08779423B2

公开(公告)日：2014-07-15

申请号：US13652812

申请日：2012-10-16

Applicant: Jiquan Liu ,  Shengan Xiao ,  Wei Ji

Inventor： Jiquan Liu ,  Shengan Xiao ,  Wei Ji

IPC: H01L29/04

CPC classification number: H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.

Abstract translation: 提供了制造半导体结构的方法。 该方法包括提供半导体衬底，在半导体衬底的顶表面上形成具有预定厚度的外延层，并在外延层中形成多个沟槽。 沟槽形成在外延层中并且具有预定的深度，顶部宽度和底部宽度。 此外，该方法包括：使用至少包含硅源气体和卤素气体的混合气体，进行沟槽内部形成半导体层的第一沟槽填充处理，当至少一个沟槽未完全填充时停止第一沟槽填充处理， 并且执行与第一沟槽填充处理不同的第二沟槽填充处理，以完全填充多个沟槽。

公开(公告)号：US20110287613A1

公开(公告)日：2011-11-24

申请号：US13106778

申请日：2011-05-12

Applicant: Jiquan Liu ,  Shengan Xiao

Inventor： Jiquan Liu ,  Shengan Xiao

IPC: H01L21/20

CPC classification number: H01L21/02532 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7802

Abstract: A manufacturing method of superjunction structure is disclosed. After the growth of an epitaxial layer on a substrate, deep trenches are etched in the epitaxial layer. A mixture of silicon source gas, hydrogen gas, halide gas and doping gas is used for trench tilling by means of epitaxial growth. The epitaxial growth rate on trench sidewalls near the bottom of the trench is set to be higher than that near the top of the trench by adjusting the flow rates of the silicon source gas and the halide gas and other parameters. By changing the flow rate of the doping gas at different stages of the epitaxial filling process, the trenches can be filled with epitaxial layers of different doping concentrations, with higher doping concentration near the bottom and lower doping concentration near the top.

Abstract translation: 公开了一种超结构结构的制造方法。 在衬底上生长外延层之后，在外延层中蚀刻深沟槽。 通过外延生长，将硅源气体，氢气，卤化物气体和掺杂气体的混合物用于沟槽耕作。 通过调整硅源气体和卤化物气体的流量等参数，将沟槽底部附近的沟槽侧壁上的外延生长率设定为高于沟槽顶部附近的外延生长速度。 通过改变外延填充过程不同阶段的掺杂气体的流速，可以用不同掺杂浓度的外延层填充沟槽，靠近底部的掺杂浓度越高，顶部附近的掺杂浓度越低。

公开(公告)号：US08653586B2

公开(公告)日：2014-02-18

申请号：US13603658

申请日：2012-09-05

Applicant: Shengan Xiao

Inventor： Shengan Xiao

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7811

Abstract: A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device.

Abstract translation: 公开了一种超结装置，其中有源区中的P型区不与N +衬底接触，并且N +衬底的表面与有源区中的P型区的底部之间的距离大于 N型外延层中的过渡区的厚度。 还公开了用于制造超结装置的方法。 本发明能够提高超级结装置中的反向击穿电压和过冲处理能力的均匀性。

公开(公告)号：US20110316121A1

公开(公告)日：2011-12-29

申请号：US13167450

申请日：2011-06-23

Applicant: Fei Wang ,  Shengan Xiao ,  Wensheng Qian

Inventor： Fei Wang ,  Shengan Xiao ,  Wensheng Qian

IPC: H01L21/20 ,  H01L29/06

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

Abstract: A method for manufacturing trench type super junction device is disclosed. The method includes the step of forming one or more P type implantation regions in the N type epitaxial layer below the bottom of each trench. By using this method, a super junction device having alternating P type and N type regions is produced, wherein the P type region is formed by P type silicon filled in the trench and P type implantation regions below the trench. The present invention can greatly improve the breakdown voltage of a super junction MOSFET.

Abstract translation: 公开了一种用于制造沟槽型超结装置的方法。 该方法包括在每个沟槽的底部下方的N型外延层中形成一个或多个P型注入区的步骤。 通过使用该方法，制造具有交替的P型和N型区域的超接合器件，其中P型区域由填充在沟槽中的P型硅和沟槽下方的P型注入区域形成。 本发明可以大大提高超结MOSFET的击穿电压。

公开(公告)号：US20110006304A1

公开(公告)日：2011-01-13

申请号：US12832963

申请日：2010-07-08

Applicant: Shengan Xiao ,  Feng Han

Inventor： Shengan Xiao ,  Feng Han

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L29/7802 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/66712

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract translation: 本发明涉及具有交替排列的P型和N型薄型半导体层的半导体器件及其制造方法。 对于P型器件，该方法包括沟槽形成，沟槽侧壁上的热氧化物形成，沟槽中的N型硅形成，通过热氧化物的N型杂质扩散到P型外延层中，沟槽中的N型硅的氧化 和氧化物去除。 在半导体装置中，N型薄型半导体层通过氧化物的N型杂质扩散形成P型外延层，并且沟槽填充有氧化物。 通过这种方法，可以通过当前的大规模生产过程实现高压装置中相对低浓度的杂质，并且降低了器件开发成本和制造成本。

公开(公告)号：US20110241156A1

公开(公告)日：2011-10-06

申请号：US13080582

申请日：2011-04-05

Applicant: Shengan Xiao

Inventor： Shengan Xiao

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L29/7802 ,  H01L29/04 ,  H01L29/0634 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66712

Abstract: Methods for manufacturing a semiconductor device with alternating P type and N type semiconductor conductive regions are disclosed. One method includes forming a trench in an N type epitaxial layer; forming carbon-contained silicon layer on sidewalls of the trench; and filling the trench with P type semiconductor layer. In another method, the carbon-contained silicon layer is replaced by a carbon film formed by diffusion process. The carbon-contained silicon layer or the carbon film can effectively inhibit the diffusion of P type impurities into the N type semiconductor layers. Further, a semiconductor device having carbon-contained layer or carbon film formed between P type and N type conductive layers is also disclosed.

Abstract translation: 公开了具有交替P型和N型半导体导电区域的半导体器件的制造方法。 一种方法包括在N型外延层中形成沟槽; 在沟槽的侧壁上形成含碳的硅层; 并用P型半导体层填充沟槽。 在另一种方法中，含碳的硅层由通过扩散工艺形成的碳膜代替。 含碳硅层或碳膜可以有效地抑制P型杂质向N型半导体层的扩散。 此外，还公开了在P型和N型导电层之间形成的含碳层或碳膜的半导体器件。

公开(公告)号：US20110241110A1

公开(公告)日：2011-10-06

申请号：US13076289

申请日：2011-03-30

Applicant: Shengan Xiao ,  Fei Wang ,  Yanping Liu

Inventor： Shengan Xiao ,  Fei Wang ,  Yanping Liu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7811

Abstract: A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed.

Abstract translation: 公开了一种超结装置的端子结构。 端子结构包括至少一个P型注入环和形成在N型外延层中的多个P型沟槽，以形成交替的P型和N型区。 在设备的边界处形成通道切断环。 P型注入环邻近器件的有源区形成并且覆盖至少一个沟槽环。 形成端子电介质层以覆盖P型注入环和沟槽环。 多个场板形成在端子电介质层的上方。 还公开了端子结构的制造方法。

公开(公告)号：US20130082323A1

公开(公告)日：2013-04-04

申请号：US13608491

申请日：2012-09-10

Applicant: Shengan Xiao

Inventor： Shengan Xiao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the P-type pillars (4) have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars (4) close to the substrate (8) is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.

Abstract translation: 公开了具有不均匀掺杂的P型柱（4）和N型柱（2a）的超结构结构。 N型柱（2a）在垂直方向上具有不均匀的杂质浓度，并且P型柱（4）具有在垂直和横向方向分布的两种或更多种杂质浓度，以确保P型杂质的总量 靠近基板（8）的P型支柱（4）的尺寸小于靠近基板的N型支柱中的N型杂质的尺寸; 靠近装置的P型支柱中的P型杂质的总量大于靠近顶部的N型支柱中的N型杂质的总量。 还公开了超结MOS晶体管及其制造方法。 超结构结构可以提高维持器件电流浪涌的能力，而不影响或甚至可以降低器件的导通电阻。

公开(公告)号：US08178409B2

公开(公告)日：2012-05-15

申请号：US12832963

申请日：2010-07-08

Applicant: Shengan Xiao ,  Feng Han

Inventor： Shengan Xiao ,  Feng Han

IPC: H01L29/15 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/66712

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract translation: 本发明涉及具有交替排列的P型和N型薄型半导体层的半导体器件及其制造方法。 对于P型器件，该方法包括沟槽形成，沟槽侧壁上的热氧化物形成，沟槽中的N型硅形成，通过热氧化物的N型杂质扩散到P型外延层中，沟槽中的N型硅的氧化 和氧化物去除。 在半导体装置中，N型薄型半导体层通过氧化物的N型杂质扩散形成P型外延层，并且沟槽填充有氧化物。 通过这种方法，可以通过当前的大规模生产过程实现高压装置中相对低浓度的杂质，并且降低了器件开发成本和制造成本。

公开(公告)号：US20110306189A1

公开(公告)日：2011-12-15

申请号：US13156286

申请日：2011-06-08

Applicant: Xiaohua Cheng ,  Shengan Xiao

Inventor： Xiaohua Cheng ,  Shengan Xiao

IPC: H01L21/205

CPC classification number: H01L21/76232

Abstract: A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer.

Abstract translation: 公开了一种蚀刻和研磨深沟槽的方法，其包括：在半导体衬底上形成ONO（氧化物 - 氮化物 - 氧化物）夹层; 通过使用夹层的顶部氧化物作为停止层形成深沟槽; 去除夹层的顶部氧化物和中间SiN; 用外延膜或多晶硅膜切割深沟槽; 通过在底部氧化物层的表面停止来抛光晶片以获得平坦化的表面; 去除底部氧化物层。