Design techniques for analyzing integrated circuit device characteristics
    1.
    发明授权
    Design techniques for analyzing integrated circuit device characteristics 失效
    分析集成电路器件特性的设计技术

    公开(公告)号:US06951002B2

    公开(公告)日:2005-09-27

    申请号:US10455164

    申请日:2003-06-05

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5036 G06F17/5068

    摘要: An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.

    摘要翻译: 一种改进的集成电路设备物理设计和布局的方法和系统。 将集成电路器件的物理布局最佳地存储在数据库中,以提供集成电路器件特性的改进的分析能力。 该方法和系统使用此优化数据库评估芯片给定平面图上的功能块和去耦单元之间的本地交互,以减少内存和处理器利用率。 通过使用dI / dt和电容估计来预测局部噪声。 识别出最高噪声的区域,并通过调整相邻去耦单元的布局及其属性来采取平面图缓解措施。 在几个迭代循环中,实现了总芯片给定平面图的近似最优解。

    Systems and methods for thermal management
    2.
    发明授权
    Systems and methods for thermal management 有权
    热管理系统和方法

    公开(公告)号:US07349762B2

    公开(公告)日:2008-03-25

    申请号:US11271460

    申请日:2005-11-10

    IPC分类号: G06F17/40

    CPC分类号: G05D23/19

    摘要: Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.

    摘要翻译: 用于感测数字设备内的多个功能块的温度的系统和方法,并且以选择性地降低与一些功能块相关联的温度而不是其它功能块的方式来控制这些功能块的操作。 一个实施例包括具有多个功能块(例如处理器核)的集成电路和耦合以感测功能块的温度的一组热传感器。 集成电路包括控制电路,其被配置为从热传感器接收信号,检测功能块中的热事件并且单独地调整功能块的操作以降低导致热事件的温度。 在一个实施例中,控制电路包括耦合到每个功能块的检测/控制电路和被配置为评估检测到的热事件并且确定响应于热事件而采取的动作的热管理单元。

    Distributing Integrated Circuit Net Power Accurately in Power and Thermal Analysis
    3.
    发明申请
    Distributing Integrated Circuit Net Power Accurately in Power and Thermal Analysis 失效
    在功率和热分析中精确分配集成电路净功率

    公开(公告)号:US20090132834A1

    公开(公告)日:2009-05-21

    申请号:US11942030

    申请日:2007-11-19

    IPC分类号: G06F1/26

    摘要: A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.

    摘要翻译: 提供了一种准确分配净功率的方法,系统和计算机程序产品。 在集成电路上模拟工作负载。 为集成电路中的一组网络和一组子网确定净交换活动。 基于净交换活动生成净交换数据。 使用净交换数据和每个单独网络或子网的净电容,为每个单独的网络和每个单独的子网计算净功率值。 每个计算的净功率值被分配给驱动单个网络或子网的一组源设备中的一个,其中净功率被精确地分配。 基于将每个净功率值分配给驱动单个网络或子网的一组源设备中的一个,生成净功率分配列表。

    Digital Thermal Sensor Test Implementation Without Using Main Core Voltage Supply
    4.
    发明申请
    Digital Thermal Sensor Test Implementation Without Using Main Core Voltage Supply 失效
    数字热传感器测试实现,不使用主芯电压

    公开(公告)号:US20090125267A1

    公开(公告)日:2009-05-14

    申请号:US11937134

    申请日:2007-11-08

    IPC分类号: G01K15/00

    CPC分类号: G01K15/00 G01K15/005

    摘要: A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.

    摘要翻译: 提供了一种用于校准数字热传感器的方法和装置。 具有多个数字热传感器的处理器芯片接收模拟电压。 耦合到处理器芯片的测试电路接收时钟信号,耦合到测试电路的寄存器将每个时钟周期上的值输出到多个数字热传感器中的数字热传感器。 数字热传感器响应于数字热传感器中接收的寄存器的值等于数字热传感器的温度阈值而转换输出状态。 在转换点处的寄存器的值用于校准数字热传感器。 响应于数字热敏传感器接收到的寄存器的值不能等于数字热传感器的温度阈值,增量器会在每个时钟周期内递增寄存器的值。

    Distributing integrated circuit net power accurately in power and thermal analysis
    5.
    发明授权
    Distributing integrated circuit net power accurately in power and thermal analysis 失效
    在电源和热分析中精确分配集成电路网络功率

    公开(公告)号:US07941680B2

    公开(公告)日:2011-05-10

    申请号:US11942030

    申请日:2007-11-19

    IPC分类号: G06F1/00 G06F1/32 G06F17/50

    摘要: A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.

    摘要翻译: 提供了一种准确分配净功率的方法,系统和计算机程序产品。 在集成电路上模拟工作负载。 为集成电路中的一组网络和一组子网确定净交换活动。 基于净交换活动生成净交换数据。 使用净交换数据和每个单独网络或子网的净电容,为每个单独的网络和每个单独的子网计算净功率值。 每个计算的净功率值被分配给驱动单个网络或子网的一组源设备之一,其中净功率被精确地分配。 基于将每个净功率值分配给驱动单个网络或子网的一组源设备中的一个,生成净功率分配列表。

    Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors
    6.
    发明申请
    Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors 审中-公开
    多核处理器中自检逻辑(LBIST)故障检测方法与装置

    公开(公告)号:US20090089636A1

    公开(公告)日:2009-04-02

    申请号:US11865153

    申请日:2007-10-01

    IPC分类号: G06F11/263 G06F11/25

    CPC分类号: G01R31/318533 G06F11/2242

    摘要: A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed.

    摘要翻译: 一种利用逻辑内置自检(LBIST)技术识别多核处理器故障的方法,系统和计算机程序产品。 已经测试了具有LBIST和伪随机模式发生器(PRPG)电路的多核处理器。 由LBIST控制逻辑控制,PRPG将测试图案输入到每个设备内核的扫描链中。 在每个LBIST循环的扫描转换阶段期间,生成并执行新的测试图案。 核心中的每个扫描链产生的逻辑输出与其他核心逻辑输出进行比较。 多内核处理器内的故障是由锁存器序列中的核心产生的逻辑输出与其他内核的逻辑输出是否匹配来确定。 如果逻辑输出从锁存序列中的内核不匹配,则锁存器号,循环号和锁存值将被记录为失败。

    Digital thermal sensor test implementation without using main core voltage supply
    7.
    发明授权
    Digital thermal sensor test implementation without using main core voltage supply 失效
    数字热传感器测试实现,不使用主芯电压供应

    公开(公告)号:US08027798B2

    公开(公告)日:2011-09-27

    申请号:US11937134

    申请日:2007-11-08

    IPC分类号: G01C19/00 G01K3/00 H02H5/04

    CPC分类号: G01K15/00 G01K15/005

    摘要: A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.

    摘要翻译: 提供了一种用于校准数字热传感器的方法和装置。 具有多个数字热传感器的处理器芯片接收模拟电压。 耦合到处理器芯片的测试电路接收时钟信号,耦合到测试电路的寄存器将每个时钟周期上的值输出到多个数字热传感器中的数字热传感器。 数字热传感器响应于数字热传感器中接收的寄存器的值等于数字热传感器的温度阈值而转换输出状态。 在转换点处的寄存器的值用于校准数字热传感器。 响应于数字热敏传感器接收到的寄存器的值不能等于数字热传感器的温度阈值,增量器会在每个时钟周期内递增寄存器的值。

    Systems and methods for thermal sensing
    8.
    发明授权
    Systems and methods for thermal sensing 有权
    热感测系统和方法

    公开(公告)号:US07535020B2

    公开(公告)日:2009-05-19

    申请号:US11168591

    申请日:2005-06-28

    IPC分类号: H01L23/58

    摘要: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.

    摘要翻译: 用于以集成电路的不同部分提供有用的热测量的方式在集成电路内定位热传感器的系统和方法。 在一个实施例中,集成电路包括多个复制功能块。 单独的热传感器耦合到每个重复功能块,优选地在每个复制功能块上相同的相对位置,并且优选地在热点处。 一个实施例还包括在集成电路中的其它类型的一个或多个功能块上的热传感器。 一个实施例包括位于集成电路芯片的边缘处的冷点处的热传感器。 每个热传感器可以具有端口,以实现传感器和外部组件或设备之间的电源和接地连接或数据连接。