公开(公告)号：US07451249B2

公开(公告)日：2008-11-11

申请号：US11378852

申请日：2006-03-16

申请人： Joe P. Cowan ,  Matthew B. Lovell ,  Leith L. Johnson ,  Jonathan K. Ross

发明人： Joe P. Cowan ,  Matthew B. Lovell ,  Leith L. Johnson ,  Jonathan K. Ross

IPC分类号： G06F13/00 ,  G06F12/14

CPC分类号： G06F12/1475 ,  G06F13/28

摘要： Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.

摘要翻译： 用于允许直接存储器存取单元访问虚拟地址空间的方法和装置是通过从直接存储器存取装置接收对存储器访问的请求而实现的; 根据接收的存储器访问请求确定设备标识符; 根据所确定的设备标识符确定存储器保护模式; 以及根据确定的存储器保护模式，授权直接存储器访问单元访问存储器。

公开(公告)号：US5689660A

公开(公告)日：1997-11-18

申请号：US712225

申请日：1996-09-11

申请人： Leith L. Johnson ,  Richard Carlson

发明人： Leith L. Johnson ,  Richard Carlson

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/423

摘要： A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data at higher data rates that the bus clock speed. By transferring data more than once per clock cycle, the data transfer rate is multiplied. Another feature of the present invention is a protocol allowing a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.

摘要翻译： 一种与行业标准总线架构兼容的PC总线架构，允许设备以更高的数据速率传输总线时钟速度的数据。 通过每个时钟周期多次传输数据，数据传输速率被乘以。 本发明的另一个特征是允许数据传输的协议，其中可以由总线主设备进行数据传输请求，然后排队，使得事务在稍后的时间发生，允许总线对于其他事务是空闲的，直到 响应设备已准备好数据。

公开(公告)号：US5255373A

公开(公告)日：1993-10-19

申请号：US741712

申请日：1991-08-07

申请人： Russell C. Brockmann ,  Leith L. Johnson ,  William S. Jaffe

发明人： Russell C. Brockmann ,  Leith L. Johnson ,  William S. Jaffe

IPC分类号： G06F13/36

CPC分类号： G06F13/36

摘要： A method and apparatus to improve computer bus access time. A bus is described which has sequential control states and fixed transaction times. Without the invention, arbitration may be delayed as the bus sequences through control states. With the invention, arbitration is immediate if the bus is idle. When any transaction is initiated, a counter is initialized to the number of control states in the standard transaction time. If the counter reaches zero, the bus is idle. If the bus is not idle, a sequence of bus control states is repeated. If the bus is idle, the bus is forced to remain in an arbitration state, thereby enabling any subsequent arbitration to take place immediately.

摘要翻译： 一种提高计算机总线访问时间的方法和装置。 描述了具有顺序控制状态和固定交易时间的总线。 没有本发明，可以通过控制状态作为总线序列来延迟仲裁。 利用本发明，如果总线空闲，则立即进行仲裁。 当任何事务被启动时，计数器被初始化为标准事务时间中的控制状态数。 如果计数器达到零，则总线空闲。 如果总线不空闲，则重复一系列总线控制状态。 如果总线空闲，则总线被迫保持在仲裁状态，从而使之能够立即进行后续仲裁。

公开(公告)号：US08782779B2

公开(公告)日：2014-07-15

申请号：US11862002

申请日：2007-09-26

申请人： Chris M. Giles ,  Russ W. Herrell ,  John A. Morrison ,  Andrew R. Wheeler ,  Gerald J. Kaufman, Jr. ,  Leith L. Johnson ,  Daniel Zilavy

发明人： Chris M. Giles ,  Russ W. Herrell ,  John A. Morrison ,  Andrew R. Wheeler ,  Gerald J. Kaufman, Jr. ,  Leith L. Johnson ,  Daniel Zilavy

IPC分类号： G06F21/00 ,  G06F12/14 ,  G06F21/53 ,  G06F12/02

CPC分类号： G06F12/1491 ,  G06F12/0284 ,  G06F21/53

摘要： A system and method for achieving one or more protected regions within a computer system having multiple partitions are disclosed. In at least some embodiments, the system includes an intermediary device for use within the computer system having the multiple partitions. The intermediary device includes a fabric device, and a first firewall device capable of limiting communication of a signal based upon at least one of a source of the signal and an intended destination of the signal, the first firewall device being at least indirectly coupled to the fabric device. The intermediary device further includes a first conversion device that is one of integrated with the first firewall device and distinct from the first firewall device, and that is capable of converting between a processor address and a fabric address for use by the fabric device. In some embodiments, the various devices each include Control and Status Registers (CSRs).

摘要翻译： 公开了一种用于在具有多个分区的计算机系统内实现一个或多个受保护区域的系统和方法。 在至少一些实施例中，系统包括用于具有多个分区的计算机系统内的中间设备。 该中间设备包括一个结构设备和一个第一防火墙设备，其能够基于该信号的源和该信号的预期目的地中的至少一个来限制信号的通信，该第一防火墙设备至少间接耦合到 织物装置。 中间设备还包括第一转换设备，其是与第一防火墙设备集成并且与第一防火墙设备不同的第一转换设备，并且能够在处理器地址和结构地址之间进行转换以供结构设备使用。 在一些实施例中，各种装置各自包括控制和状态寄存器（CSR）。

公开(公告)号：US5274671A

公开(公告)日：1993-12-28

申请号：US744852

申请日：1991-08-14

申请人： Leith L. Johnson

发明人： Leith L. Johnson

IPC分类号： G06F13/40 ,  H04B3/00

CPC分类号： G06F13/4077

摘要： An output resistance (R.sub.O) is situated at each output of a plurality of drivers communicating to a plurality of receivers via an interconnect network which is biased by a terminal supply voltage (V.sub.T). The output resistance R.sub.O eliminates the need for a wait period in a cycle, which wait period is usually required when mastership of the interconnect network changes over from one driver to another driver. The drivers and receivers are two-state devices. For a logic high, the drivers exhibit a virtually infinite resistance. Consequently, the interconnect network exhibits a high voltage V.sub.INT, which is approximately equal to the terminal supply voltage V.sub.T. Whereas for a logic low, the drivers sink current from the interconnect network, thereby pulling the interconnect network voltage V.sub.INT towards ground. Any signal below about (7/8)*V.sub.T is recognized by the receivers as a logic low, while any signal above this threshold is recognized as a logic high. In the case of a logic low, the voltage V.sub.INT is prevented from being pulled to ground by the output resistance (R.sub.O). The driver sinks enough current so that the voltage V.sub.INT is approximately equal to V.sub.T /2. Accordingly, if a change over occurs in a cycle after a logic low, the newly active driver can immediately drive a logic high or low onto the interconnect network, because the voltage V.sub.T /2 is readily available on the interconnect network. If the newly active driver wishes to drive a logic high, the driver exhibits infinite resistance, and the voltage V.sub.INT increases to V.sub.T. If the newly active driver wishes to drive a logic low, the driver sinks current, and the voltage V.sub.INT increases to only about (3/4)*(V.sub.T), which is recognized as a logic low. The voltage V.sub.INT will ultimately decrease to V.sub.T /2, thereby enhancing its disposition as a logic low.

摘要翻译： 输出电阻（RO）位于通过由终端电源电压（VT）偏置的互连网络与多个接收器通信的多个驱动器的每个输出处。 输出电阻RO消除了对周期中的等待周期的需要，当互连网络的主管从一个驱动器改变到另一个驱动器时，通常需要等待周期。 驱动器和接收器是双态器件。 对于逻辑高，驱动程序呈现出几乎无限的阻力。 因此，互连网络呈现高电压VINT，其大致等于端子电源电压VT。 而对于逻辑低电平，驱动器从互连网络吸收电流，从而将互连网络电压VINT拉到地。 低于约（7/8）* VT的任何信号被接收器识别为逻辑低电平，而高于该阈值的任何信号被识别为逻辑高电平。 在逻辑低的情况下，通过输出电阻（RO）防止电压VINT被拉到地。 驱动器吸收足够的电流，使得电压VINT近似等于VT / 2。 因此，如果在逻辑低电平之后的周期内发生改变，则由于电压VT / 2在互连网络上容易获得，所以新激活的驱动器可以立即将逻辑高或低地驱动到互连网络上。 如果新启动的驱动器希望驱动逻辑高电平，则驱动器呈现无限阻力，并且电压VINT增加到VT。 如果新启动的驱动器希望驱动逻辑低电平，则驱动器吸收电流，并且电压VINT增加到只有大约（3/4）*（VT），这被识别为逻辑低电平。 电压VINT将最终降低到VT / 2，从而将其设置提高为逻辑低。

公开(公告)号：US20090083505A1

公开(公告)日：2009-03-26

申请号：US11862002

申请日：2007-09-26

申请人： Chris M. Giles ,  Russ W. Herrell ,  John A. Morrison ,  Andrew R. Wheeler ,  Gerald J. Kaufman, JR. ,  Leith L. Johnson ,  Daniel Zilavy

发明人： Chris M. Giles ,  Russ W. Herrell ,  John A. Morrison ,  Andrew R. Wheeler ,  Gerald J. Kaufman, JR. ,  Leith L. Johnson ,  Daniel Zilavy

IPC分类号： G06F12/14 ,  G06F12/02

CPC分类号： G06F12/1491 ,  G06F12/0284 ,  G06F21/53

摘要： A system and method for achieving one or more protected regions within a computer system having multiple partitions are disclosed. In at least some embodiments, the system includes an intermediary device for use within the computer system having the multiple partitions. The intermediary device includes a fabric device, and a first firewall device capable of limiting communication of a signal based upon at least one of a source of the signal and an intended destination of the signal, the first firewall device being at least indirectly coupled to the fabric device. The intermediary device further includes a first conversion device that is one of integrated with the first firewall device and distinct from the first firewall device, and that is capable of converting between a processor address and a fabric address for use by the fabric device. In some embodiments, the various devices each include Control and Status Registers (CSRs).

摘要翻译： 公开了一种用于在具有多个分区的计算机系统内实现一个或多个受保护区域的系统和方法。 在至少一些实施例中，系统包括用于具有多个分区的计算机系统内的中间设备。 该中间设备包括一个结构设备和一个第一防火墙设备，其能够基于该信号的源和该信号的预期目的地中的至少一个来限制信号的通信，该第一防火墙设备至少间接耦合到 织物装置。 中间设备还包括第一转换设备，其是与第一防火墙设备集成并且与第一防火墙设备不同的第一转换设备，并且能够在处理器地址和结构地址之间进行转换以供结构设备使用。 在一些实施例中，各种设备各自包括控制和状态寄存器（CSR）。

公开(公告)号：US20080059710A1

公开(公告)日：2008-03-06

申请号：US11514549

申请日：2006-08-31

申请人： Erin A. Handgen ,  Leith L. Johnson

发明人： Erin A. Handgen ,  Leith L. Johnson

IPC分类号： G06F12/00

CPC分类号： G06F12/0826 ,  G06F12/082

摘要： A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.

摘要翻译： 目录缓存被提供有多个目录条目，其被配置为存储关于存储在多个高速缓存中的存储器行的副本的信息。 这些条目被划分为N个条目的集合，每个N个条目的集合可通过索引寻址。 目录缓存还提供有缓存控制器。 缓存控制器检索与对应于存储器线的索引相关联的一组N个条目，并且如果检索到的条目之一的标签部分对应于存储器行，则高速缓存控制器确定所检索的条目之一是否包含指示 关于存储器线的信息被存储在所检索的条目中的至少第二个中。

公开(公告)号：US5287477A

公开(公告)日：1994-02-15

申请号：US741703

申请日：1991-08-07

申请人： Leith L. Johnson ,  Russell C. Brockmann ,  William S. Jaffe

发明人： Leith L. Johnson ,  Russell C. Brockmann ,  William S. Jaffe

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/161 ,  G06F12/0607

摘要： A method and apparatus to improve memory performance in a computer bus system. Memory is divided into interleaved blocks and memory addresses are mapped into block identification numbers. Master devices keep track of which parts of memory are busy by storing memory block identification numbers in local queues whenever memory is accessed. Block identification numbers are removed from local queues when the memory transaction is complete. Master devices arbitrate for access to the bus for memory transactions only if the target memory block identification number is not in the local queue.

摘要翻译： 一种用于改善计算机总线系统中的存储器性能的方法和装置。 存储器被划分为交错块，存储器地址被映射到块标识号。 当存储器被访问时，主设备通过将存储器块识别号码存储在本地队列中来跟踪存储器的哪个部分正在占用。 当内存事务完成时，块标识号从本地队列中删除。 只有当目标存储器块标识号不在本地队列中时，主设备仲裁才能访问总线用于存储器事务。

公开(公告)号：US07103793B2

公开(公告)日：2006-09-05

申请号：US10685940

申请日：2003-10-14

申请人： Eric M. Rentschler ,  Jeffrey G. Hargis ,  George T. Letey ,  Leith L. Johnson

发明人： Eric M. Rentschler ,  Jeffrey G. Hargis ,  George T. Letey ,  Leith L. Johnson

IPC分类号： G06F12/00 ,  G06F1/04

CPC分类号： G06F13/1689

摘要： A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).

摘要翻译： 双数据速率存储器控制器设置有多个数据和选通焊盘，用于经由所述焊盘以1x双倍数据速率存储器速度接收数据和选通信号的装置，以及用于经由所述焊盘以Mx双倍数据接收数据和选通信号的装置 速率记忆速度（M2）。

公开(公告)号：US06633965B2

公开(公告)日：2003-10-14

申请号：US09828604

申请日：2001-04-07

申请人： Eric M. Rentschler ,  Jeffrey G. Hargis ,  Leith L. Johnson

发明人： Eric M. Rentschler ,  Jeffrey G. Hargis ,  Leith L. Johnson

IPC分类号： G06F1200

CPC分类号： G06F13/1689

摘要： Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.

摘要翻译： 本文公开了从存储器接收数据的方法和装置，与选通相关联的数据。 通常，所述方法和装置为存储器控制器提供了以不同速率接收数据的装置。 数据可以由存储器控制器以不同的速率接收，因为例如，存储器控制器用于其直接连接到多个存储器模块的环境中，和/或在其经由多个存储器模块附接到多个存储器模块的环境中使用 中介芯片 中间芯片可以例如包括从两个或多个存储器模块组接收数据的多路复用器，然后将数据复用到一个或多个数据流中，然后将数据流以两倍于存储器模块的速率传输到存储器控制器 银行可以将数据发送到内存控制器。