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1.发明授权Method and apparatus for direct input and output in a virtual machine environment containing a guest operating system 有权用于在包含客户机操作系统的虚拟机环境中直接输入和输出的方法和装置公开(公告)号：US07451249B2
公开(公告)日：2008-11-11
申请号：US11378852
申请日：2006-03-16
CPC分类号： G06F12/1475 , G06F13/28
摘要： Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.
摘要翻译： 用于允许直接存储器存取单元访问虚拟地址空间的方法和装置是通过从直接存储器存取装置接收对存储器访问的请求而实现的; 根据接收的存储器访问请求确定设备标识符; 根据所确定的设备标识符确定存储器保护模式; 以及根据确定的存储器保护模式，授权直接存储器访问单元访问存储器。
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2.发明授权Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统公开(公告)号：US07281116B2
公开(公告)日：2007-10-09
申请号：US10903200
申请日：2004-07-30
申请人： Jonathan K. Ross , Dale Morris
发明人： Jonathan K. Ross , Dale Morris
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/682
摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.
摘要翻译： 本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。 与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。 因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。
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公开(公告)号：US07272702B2
公开(公告)日：2007-09-18
申请号：US10702252
申请日：2003-11-06
IPC分类号： G06F9/34
CPC分类号： G06F9/30123 , G06F9/30134 , G06F9/384 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.
摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。
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公开(公告)号：US07613847B2
公开(公告)日：2009-11-03
申请号：US11435831
申请日：2006-05-16
CPC分类号： G06F12/1081 , G06F9/45558 , G06F2009/45579 , H04L67/08
摘要： A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.
摘要翻译： 计算机系统包括物理计算机和可在物理计算机上执行的虚拟机监视器，并且被配置为创建适于控制物理计算机的至少一个客户操作系统的仿真。 计算机系统还包括在物理计算机上可执行的主机，其代表虚拟机监视器和至少一个客户操作系统管理耦合到物理计算机的物理资源。 主机适于虚拟化外围组件互连（PCI）配置地址空间，由此至少一个客户操作系统直接控制PCI输入/输出（I / O）设备，并且在没有I / O仿真的情况下。
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公开(公告)号：US07426728B2
公开(公告)日：2008-09-16
申请号：US10670026
申请日：2003-09-24
CPC分类号： G06F9/30101 , G06F9/30116 , G06F9/3863
摘要： One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.
摘要翻译： 公开的一个实施例涉及一种减少对微处理器内的本地可编程中断控制器单元的任务优先级寄存器（TPR）的访问等待时间的方法。 接收到向TPR写入中断屏蔽值的命令，并将中断屏蔽值写入TPR。 此外，中断屏蔽值也被写入TPR的卷影副本。 每次写入TPR时都会写入影子副本。 所公开的另一实施例涉及一种减少读取IPF型微处理器的TPR的等待时间的方法。 当接收到从TPR读取中断屏蔽值的命令时，中断屏蔽值将从存储器位置的卷影副本中读取，而不是从任务优先级寄存器本身读取。
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6.发明授权Method and apparatus for transferring data between a register stack and a memory resource 失效用于在寄存器堆栈和存储器资源之间传送数据的方法和装置公开(公告)号：US06263401B1
公开(公告)日：2001-07-17
申请号：US08940834
申请日：1997-09-30
IPC分类号： G06F9315
CPC分类号： G06F9/463 , G06F9/30105 , G06F9/30127 , G06F9/30134
摘要： A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register. Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.
摘要翻译： 描述了一种用于将寄存器堆栈中的通用寄存器的内容传送到主存储器中的后备存储器中的位置的计算机实现的方法和装置。 当将通用寄存器的内容传送到后备存储器中的位置时，本发明提出收集临时收集寄存器中预定寄存器组的每个通用寄存器中包含的属性位。 一旦临时收集寄存器被填写，该寄存器的内容将被写入后备存储中的下一个可用位置。 类似地，在从后台存储器恢复寄存器时，保存在后备寄存器中的属性位的集合被传送到临时收集寄存器。 此后，每个属性位与相关联的数据一起保存到通用寄存器中，从而恢复每个通用寄存器的前一个内容。
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7.发明授权Code sequence for asynchronous backing store switch utilizing both the cover and LOADRS instructions 失效使用封面和LOADRS指令的异步后备存储开关的代码序列
公开(公告)号：US6112292A
公开(公告)日：2000-08-29
申请号：US64025
申请日：1998-04-21
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/30134
摘要： A computer implemented method for switching from an interrupted context to an interrupting context in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) that exchanges information, in one of instruction execution dependent and independent modes between the second portion and a storage area. The method includes the following steps: a state of the RSE of the interrupted context is preserved; a COVER instruction is issued; a first (BSPSTORE) pointer is preserved. The first pointer points to a location in the storage area, of the interrupted context, where a next register of the second portion is to be written; first pointer is written with a value corresponding to the interrupting context; and a second pointer (BSP) is preserved. The new first and second pointers in the interrupting context define the storage area of RS values associated with the interrupted context. The new first pointer is subtracted from the second new pointer. The difference (number of dirty registers) is deposited into the RSC.loadrs field. A LOADRS instruction is issued to load the RS with all interrupted context values. The original first BSPSTORE is restored from the preserved BSPSTORE.
摘要翻译： 提供了一种用于从中断的上下文切换到处理器中的中断上下文的计算机实现的方法。 处理器包括具有第一和第二部分的寄存器堆栈（RS）。 处理器包括在第二部分和存储区域之间以指令执行相关的和独立的模式之一交换信息的寄存器堆栈引擎（RSE）。 该方法包括以下步骤：保持中断上下文的RSE状态; 发出COVER指令; 第一个（BSPSTORE）指针被保留。 第一指针指向存储区域中断上下文的位置，其中第二部分的下一个寄存器将被写入; 第一个指针用与中断上下文相对应的值写入; 并保留第二个指针（BSP）。 中断上下文中的新的第一和第二指针定义与中断上下文相关联的RS值的存储区域。 从第二个新指针中减去新的第一个指针。 差异（脏寄存器数）被存入RSC.loadrs字段。 发出LOADRS指令以加载具有所有中断上下文值的RS。 原始的第一个BSPSTORE从保存的BSPSTORE恢复。
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公开(公告)号：US20080270349A1
公开(公告)日：2008-10-30
申请号：US11799429
申请日：2007-04-30
IPC分类号： G06F7/00
CPC分类号： G06F17/3033 , G06F12/1018
摘要： A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.
摘要翻译： 公开了一种在虚拟散列页表内映射活动条目的方法。 虚拟散列页表中的活动条目将被填充。 用于定位与活动条目偏移处的链接的链接表保持不变。 该链接表继续维持为有效的链接表，直到超过占用的头桶阈值或发生了冲突。
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公开(公告)号：US06665793B1
公开(公告)日：2003-12-16
申请号：US09473820
申请日：1999-12-28
IPC分类号： G06F9312
CPC分类号： G06F9/30123 , G06F9/30134 , G06F9/384 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.
摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。
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公开(公告)号：US06505296B2
公开(公告)日：2003-01-07
申请号：US09521160
申请日：2000-03-08
IPC分类号： G06F942
CPC分类号： G06F9/3834 , G06F8/445 , G06F9/3838 , G06F9/3842 , G06F9/3861 , G06F11/1407
摘要： A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.
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