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公开(公告)号：US07772918B2
公开(公告)日：2010-08-10
申请号：US12104132
申请日：2008-04-16
CPC分类号： H02M3/07 , H02M2001/0045
摘要： An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.
摘要翻译： 一种用于集成电路（IC）装置的稳压升压电荷泵的装置和方法。 电荷泵通常包括间歇地耦合到输出电容器或调节晶体管的多个开关网络和升压电容器，偏置晶体管的栅极端子的差分误差放大器以及配置成交替转换开关状态的控制器 所述交换网络与所述IC设备的时钟信号处于预先选择的定时关系。
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公开(公告)号：US20090261890A1
公开(公告)日：2009-10-22
申请号：US12104132
申请日：2008-04-16
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2001/0045
摘要： An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.
摘要翻译： 一种用于集成电路（IC）装置的稳压升压电荷泵的装置和方法。 电荷泵通常包括间歇地耦合到输出电容器或调节晶体管的多个开关网络和升压电容器，偏置晶体管的栅极端子的差分误差放大器以及配置成交替转换开关状态的控制器 所述交换网络与所述IC设备的时钟信号处于预先选择的定时关系。
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公开(公告)号：US07675806B2
公开(公告)日：2010-03-09
申请号：US11435942
申请日：2006-05-17
申请人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russell , Shayan Zhang , Michael Snyder
发明人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russell , Shayan Zhang , Michael Snyder
IPC分类号： G11C5/14
摘要： A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
摘要翻译： 公开了一种具有低电压存储器件的器件。 该设备包括具有第一存储器拓扑的第一存储器和具有第二存储器拓扑的第二存储器，其中两个存储器位于集成电路中。 第一存储器是相对高密度存储器件，能够存储相对于第二存储器的大量数据。 第二存储器是能够相对于可以访问第一存储器的电压的低电压访问的低电压存储器件。 因此，当集成电路处于低电压工作模式时，第二存储器可访问，这可以表示第一存储器或集成电路的其它部分的数据保持状态（睡眠状态）。 因此，该器件能够在正常或主动操作模式下将大量数据存储在高密度存储器中，并且还可以在低电压操作模式期间访问低电压存储器。
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公开(公告)号：US07532142B1
公开(公告)日：2009-05-12
申请号：US12139318
申请日：2008-06-13
IPC分类号： H03M1/78
CPC分类号： H03M1/0602 , H03M1/765
摘要： A digital to analog converter (DAC) system includes a resistor network providing enhanced response time and steady state characteristics.
摘要翻译： 数模转换器（DAC）系统包括一个提供增强的响应时间和稳态特性的电阻网络。
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公开(公告)号：US20070280026A1
公开(公告)日：2007-12-06
申请号：US11435942
申请日：2006-05-17
申请人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russel , Shayan Zhang , Michael Snyder
发明人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russel , Shayan Zhang , Michael Snyder
IPC分类号： G11C5/14
摘要： A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
摘要翻译： 公开了一种具有低电压存储器件的器件。 该设备包括具有第一存储器拓扑的第一存储器和具有第二存储器拓扑的第二存储器，其中两个存储器位于集成电路中。 第一存储器是相对高密度存储器件，能够存储相对于第二存储器的大量数据。 第二存储器是能够相对于可以访问第一存储器的电压的低电压访问的低电压存储器件。 因此，当集成电路处于低电压工作模式时，第二存储器可访问，这可以表示第一存储器或集成电路的其它部分的数据保持状态（睡眠状态）。 因此，该设备能够在正常或主动操作模式下将大量数据存储在高密度存储器中，并且还可以在低电压操作模式期间访问低电压存储器。
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6.发明申请Memory and method for sensing data in a memory using complementary sensing scheme 有权用于使用互补感测方案检测存储器中的数据的存储器和方法公开(公告)号：US20070171747A1
公开(公告)日：2007-07-26
申请号：US11337783
申请日：2006-01-23
申请人： Bradford Hunter , Shayan Zhang
发明人： Bradford Hunter , Shayan Zhang
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译： 在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。 所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。 差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。 全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。
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公开(公告)号：US20070171713A1
公开(公告)日：2007-07-26
申请号：US11337775
申请日：2006-01-23
申请人： Bradford Hunter , James Burnett , Jack Higman
发明人： Bradford Hunter , James Burnett , Jack Higman
IPC分类号： G11C16/04
CPC分类号： G11C11/412 , G11C11/413
摘要： An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage. This bi-directional low voltage drop low loss switch can increase the write margin of the memory cell wherein the high impedance read port can provide increased isolation for the stored value during the read phase increasing the performance of the memory cell.
摘要翻译： 电子设备包括存储单元，其利用双向低阻抗低压降全通栅极在写入阶段期间将位单元连接到位写入线，并且在读取阶段期间，全通道栅极可以保持关断，并且 高输入阻抗读取端口可以获取和传输存储器单元存储的逻辑状态到另一个子系统。 可以通过与NMOS器件并联连接P型金属半导体场效应晶体管（PMOS）并用差分信号驱动晶体管的栅极来实现全通栅。 当写入操作需要电流沿第一方向流动时，PMOS器件提供可忽略的电压降，并且当写操作需要电流在第二或相反方向上流动时，NMOS器件可以提供可忽略的电压。 该双向低压降低损耗开关可以增加存储单元的写入裕度，其中高阻抗读取端口可以在读取阶段期间为存储的值提供增加的隔离以增加存储单元的性能。
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公开(公告)号：US20070080730A1
公开(公告)日：2007-04-12
申请号：US11245566
申请日：2005-10-07
申请人： Bradford Hunter
发明人： Bradford Hunter
IPC分类号： H03K5/12
摘要： In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.
摘要翻译： 根据本公开，集成电路的电子电路被配置为接收具有下降转换和上升转换的输入信号，并且在其输出上提供输入信号转换的可选延迟。 所公开的电路的输出可以提供响应于下降沿控制信号控制而延迟的下降转换，以及响应于上升沿控制信号而延迟的上升转变。 所公开的电路可以具有上升跃迁控制电路（RTCC），下降跃迁控制电路（FTCC）和输出电路。
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