-
公开(公告)号：US20090261890A1
公开(公告)日：2009-10-22
申请号：US12104132
申请日：2008-04-16
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2001/0045
摘要： An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.
摘要翻译： 一种用于集成电路（IC）装置的稳压升压电荷泵的装置和方法。 电荷泵通常包括间歇地耦合到输出电容器或调节晶体管的多个开关网络和升压电容器，偏置晶体管的栅极端子的差分误差放大器以及配置成交替转换开关状态的控制器 所述交换网络与所述IC设备的时钟信号处于预先选择的定时关系。
-
公开(公告)号：US07772918B2
公开(公告)日：2010-08-10
申请号：US12104132
申请日：2008-04-16
CPC分类号： H02M3/07 , H02M2001/0045
摘要： An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.
摘要翻译： 一种用于集成电路（IC）装置的稳压升压电荷泵的装置和方法。 电荷泵通常包括间歇地耦合到输出电容器或调节晶体管的多个开关网络和升压电容器，偏置晶体管的栅极端子的差分误差放大器以及配置成交替转换开关状态的控制器 所述交换网络与所述IC设备的时钟信号处于预先选择的定时关系。
-
3.发明授权公开(公告)号：US06552944B2
公开(公告)日：2003-04-22
申请号：US09870755
申请日：2001-05-31
IPC分类号： G11C702
CPC分类号： G11C7/067 , G11C7/062 , G11C11/4091
摘要： A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array.
摘要翻译： 单个位线直接感测架构采用位于每个存储器阵列中的4晶体管读出放大器电路，其中晶体管用于选择性地将数据位从位线对的真位置或补码位线传送到数据线。 数据线优选地布置在多个存储器阵列上。 读取和写入操作可能共享或不共享数据行。 一个电流源另外用于在读取模式下对数据进行预充电，通过检测电流源和由相应阵列的位线驱动的晶体管之间的电阻比来执行数字感测方案的功能。 可以使用简单的逆变器来检测由电阻比确定的数据线的电平。 以单端方式检测位线对，消除了对交叉耦合的CMOS器件的需要，从而减少了所需的布局面积。 通过单独访问位线对，开发了用于预充电EQ0，EQ1的两组控制信号，以允许阵列中的位线屏蔽。
-
4.发明授权公开(公告)号：US06445611B1
公开(公告)日：2002-09-03
申请号：US09966142
申请日：2001-09-28
IPC分类号： G11C1124
CPC分类号： G11C8/08 , G11C11/4076 , G11C11/408 , G11C2207/104
摘要： An arrangement and method is disclosed which works toward shortening the machine cycle of a DRAM. A data value is written to a storage capacitor of a memory cell of the DRAM, the data value being stored in the storage capacitor as one of low state and high state. During a first wordline activation cycle, a storage capacitor is preconditioned to a preconditioned voltage level. In a subsequent wordline activation cycle, a low state or a high state is written to the storage capacitor. In an aspect of the invention, the wordline is activated in a first wordline activation cycle to begin clearing any previously stored state of the storage capacitor. This cycle may include the reading of a stored data value from the storage capacitor. Then, immediately thereafter, while maintaining the wordline activated, the storage capacitor is preconditioned to a preconditioned voltage level, as by clamping the bitline through a bitline restore device. The wordline is then deactivated. Subsequently, the wordline is activated again during a write cycle to write one of a low state and a high state to the storage capacitor to indicate a stored data value.
摘要翻译： 公开了用于缩短DRAM的机器周期的布置和方法。 将数据值写入到DRAM的存储单元的存储电容器中，将数据值存储在存储电容器中作为低状态和高状态之一。 在第一字线激活周期期间，存储电容器被预处理成预处理的电压电平。 在随后的字线激活周期中，将低状态或高状态写入存储电容器。在本发明的一个方面，字线在第一字线激活周期中被激活，以开始清除存储电容器的任何先前存储的状态。 该周期可以包括从存储电容器读取存储的数据值。 然后，紧接其后，在保持字线被激活的同时，将存储电容器预先处理为预处理的电压电平，如通过位线恢复装置夹紧位线。 然后禁用字线。 随后，在写入周期期间再次激活字线以将低状态和高状态中的一个写入存储电容器以指示存储的数据值。
-
公开(公告)号：US06711078B2
公开(公告)日：2004-03-23
申请号：US10064306
申请日：2002-07-01
IPC分类号： B11C700
CPC分类号： G11C11/40615 , G11C7/065 , G11C7/1051 , G11C7/1069 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.
摘要翻译： 用于直接感测架构存储器的回写和刷新电路，其中多个主感测放大器连接到全局数据线，并且还连接到位线，每个位线被耦合到被选择用于写入和读取操作的存储器存储单元的阵列 通过多个字线。 单个次级感测放大器从全局数据线上的主感测放大器接收模拟电平数据，并且包括恢复/回写电路，其对数据进行数字化，然后将数字化数据通过全局数据线返回到主感测放大器并且返回 记忆。 每个存储器读取周期，第一周期读取操作和第二个周期回写操作都使用2周期读/写操作。 2周期的破坏性读取架构不需要缓存和复杂的缓存算法。
-
公开(公告)号：US06438051B1
公开(公告)日：2002-08-20
申请号：US09870559
申请日：2001-05-31
申请人： John A. Fifield , Wing K. Luk , Daniel W. Storaska
发明人： John A. Fifield , Wing K. Luk , Daniel W. Storaska
IPC分类号： G11C704
摘要： A stabilized direct sensing memory architecture which provides Process, Voltage and Temperature (PVT) compensation in a memory array to a direct sense circuit to increase the manufacturing yield thereof, and to extend the operating voltage and temperature ranges thereof independent of manufacturing tolerances. A single-ended sense amplifier structure has a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal superimposed on a bitline precharge voltage. A mimic bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.
摘要翻译： 一种稳定的直接感测存储器架构，其将存储器阵列中的过程，电压和温度（PVT）补偿提供给直接感测电路以增加其制造产量，并且独立于制造公差来扩展其工作电压和温度范围。 单端读出放大器结构具有由PFET提供的可调电流源负载的公共源NFET放大器。 自动调整PFET电流源，使NFET放大器处于工作范围，以提供叠加在位线预充电电压上的小信号的最大放大。 模拟偏置发生器电路提供该工作点调整，并且使用少量晶体管实现直接的单端感测操作。
-
公开(公告)号：US08724365B2
公开(公告)日：2014-05-13
申请号：US13427162
申请日：2012-03-22
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
-
8.发明申请MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERENT TEMPERATURE COEFFICIENTS 有权具有开启和关闭状态的存储器阵列具有不同温度系数的字线电压公开(公告)号：US20140003164A1
公开(公告)日：2014-01-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译： 公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。 为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。 在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。 还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。 还公开了一种操作存储器阵列结构的方法。
-
公开(公告)号：US08027207B2
公开(公告)日：2011-09-27
申请号：US12639454
申请日：2009-12-16
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C17/16 , G11C5/147 , G11C7/062 , G11C7/12 , G11C17/18 , G11C29/02 , G11C29/021 , G11C29/028
摘要： An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.
摘要翻译： 电熔丝感测电路采用单端感测方案，其中参考电压被补偿以进行泄漏。 参考电压发生器包括与所选位线上拉电阻相似的上拉电阻。 由于通过选择位线上拉电阻来调整感测跳变点，一对上拉电阻和下拉电阻一起调节，以调整参考电压发生器的阻抗。 包括比特单元的并联连接的泄漏路径模拟结构被添加到参考电压发生器。 泄漏路径模拟结构模仿电子熔丝阵列中的位线上的位单元。 位线上的漏电流将位线电压抵消一定的误差电压。 在存在泄漏的情况下，参考电压也被误差电压的一部分偏移以平衡'1'和'0'余量水平的偏移。
-
10.发明授权公开(公告)号：US07917806B2
公开(公告)日：2011-03-29
申请号：US11958680
申请日：2007-12-18
IPC分类号： G06F11/00
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译： 多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。 接收数字符合性信号，每个合规信号与多个片上电源之一相关联。 每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。 合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。 输出电源状态信号。 如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。 如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。 如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。
-
-
-
-
-
-
-
-
-
搜索结果
167 条记录 (耗时 0.03 秒)