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    Fault containment system for multiprocessor with shared memory
    8.
    发明授权
    Fault containment system for multiprocessor with shared memory 失效
    具有共享内存的多处理器故障容错系统

    公开(公告)号：US5761413A

    公开(公告)日：1998-06-02

    申请号：US462759

    申请日：1995-06-05

    申请人： Steven J. Frank ,  William F. Mann

    发明人： Steven J. Frank ,  William F. Mann

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F11/00 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  H04L12/46 ,  H04L12/56

    CPC分类号： G06F9/5016 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/10 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  H04L12/4637 ,  H04L45/04 ,  G06F12/126 ,  G06F2212/272 ,  H04L2012/562

    摘要： A multiprocessor system has a plurality of processing cells, each including a processor and memory, interconnected via a network. The memories respond to requests by the processors for accessing data and, absent fault, transmitting it in response packets to at least to the requesting processors. A fault containment element responds to at least certain faults during access or transmission of a datum for including within the respective response packet a fault signal that prevents the requestor from accessing the datum. If a fault is detected in a datum not previously detected as faulty, a marking element can include a "marked fault" signal in the response packet. Whereas, it can include an "unmarked fault" signal when it detects a fault associated with a requested datum, but not specifically isolated to that datum. When a request is made for a datum which had previously been detected as faulty, the marking element can include in the response packet a "descriptor fault" signal. This facilitates identification of a particular source of an error and prevents that error from propagating to other processing cells.

    摘要翻译： 多处理器系统具有多个处理单元，每个处理单元包括通过网络互连的处理器和存储器。 存储器响应处理器访问数据的请求，并且在没有故障的情况下，响应分组将其发送到至少到请求处理器。 故障容纳元件在访问或传输数据期间响应于至少某些故障，以在相应的响应分组内包括阻止请求者访问基准的故障信号。 如果在以前未被检测为故障的原点中检测到故障，则标记元件可以在响应分组中包括“标记故障”信号。 而当它检测到与所请求的数据相关联的故障时，可以包括“未标记的故障”信号，但不特别地与该数据隔离。 当对先前被检测为故障的原点作出请求时，标记元件可以在响应包中包括“描述符故障”信号。 这有助于识别错误的特定源，并防止该错误传播到其他处理单元。

    Hierarchical cache memory system and method
    10.
    发明授权
    Hierarchical cache memory system and method 失效
    分层缓存系统和方法

    公开(公告)号：US4755930A

    公开(公告)日：1988-07-05

    申请号：US749581

    申请日：1985-06-27

    申请人： Andrew W. Wilson, Jr. ,  Steven J. Frank

    发明人： Andrew W. Wilson, Jr. ,  Steven J. Frank

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0897 ,  G06F12/0811 ,  G06F12/0831

    摘要： A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.

    摘要翻译： 一种用于共享总线多处理器的缓存系统，其包括几个处理器，每个处理器具有其自己的专用高速缓冲存储器。 每个专用高速缓存连接到第二总线，第二高级缓存存储器也连接到第一总线。 第二个更高级别的缓存又通过全局总线连接到另一个总线和更高级别的高速缓存或主系统存储器。 每个高级缓存都包含足够的内存空间，以便使更高级别的缓存能够在其正下方的缓存中的高速缓存中具有每个内存位置的副本。 反过来，主存储器包括用于最高级别的高速缓冲存储器的每个存储器位置的副本的足够的空间。 缓存可以与直写或写延迟缓存一致性管理方案一起使用。