公开(公告)号：US06660330B2

公开(公告)日：2003-12-09

申请号：US09829648

申请日：2001-04-10

申请人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

发明人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

IPC分类号： C23C1606

CPC分类号： C23C16/466 ,  C23C16/481 ,  H01L21/28556 ,  H01L21/67109

摘要： The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.

摘要翻译： 本发明涉及一种在基板表面上的金属膜的低压化学气相沉积（CVD）期间确保变形耐受基板的均匀可重复加热的方法和装置。 在本发明中通过将衬底定位在位于CVD反应器室中的加热元件上方的倒角环的斜面上来实现衬底的均匀和可再现的加热。 加热元件，倒角环和衬底底面之间的空间限定了衬底和加热元件之间的空腔，确保衬底被辐射装置加热而不是直接接触。

公开(公告)号：US06380075B1

公开(公告)日：2002-04-30

申请号：US09676546

申请日：2000-09-29

申请人： Cyril Cabral, Jr. ,  Chao-Kun Hu ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon

发明人： Cyril Cabral, Jr. ,  Chao-Kun Hu ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871

摘要： A method for forming an open-bottom liner for a conductor in an electronic structure and devices formed are disclosed. In the method, a pre-processed electronic substrate that has a dielectric layer on top is first provided. Via openings are then formed in a dielectric layer to expose an underlying conductive layer. The electronic substrate is then positioned in a cold-wall, low pressure chemical vapor deposition chamber, while the substrate is heated to a temperature of at least 350° C. A precursor gas is then flowed into the CVD chamber to a partial pressure of not higher than 10 mTorr, and metal is deposited from the precursor gas onto sidewalls of the via openings while bottoms of the via openings are substantially uncovered by the metal. The present invention method may be further enhanced by, optionally, modifications of a I-PVD technique or a seed layer deposition technique.

摘要翻译： 公开了一种用于形成电子结构中的导体的开口底部衬垫和形成的器件的方法。 在该方法中，首先提供在顶部具有电介质层的预处理电子基板。 然后在电介质层中形成通孔以暴露下面的导电层。 然后将电子基板定位在冷壁低压化学气相沉积室中，同时将基板加热至至少350℃的温度。然后将前体气体流入CVD室至不分压 高于10mTorr，并且金属从前体气体沉积到通孔开口的侧壁上，而通路孔的底部基本上不被金属覆盖。 本发明的方法可以通过任选地修饰I-PVD技术或种子层沉积技术进一步增强。

公开(公告)号：US06211042B1

公开(公告)日：2001-04-03

申请号：US09170621

申请日：1998-10-13

申请人： Fenton Read McFeely ,  Ismail Cevdet Noyan ,  John Jacob Yurkas

发明人： Fenton Read McFeely ,  Ismail Cevdet Noyan ,  John Jacob Yurkas

IPC分类号： H01L2120

CPC分类号： H01L21/28518 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： A method is disclosed for forming an epitaxial layer of a semiconductor material over a metal structure disposed upon a surface of a semiconductor substrate, the metal being characterized by a negative Gibbs free energy for the formation of a compound of the metal and the semiconductor material. The method comprises the steps of: a) placing the substrate in a reactor vessel having a base pressure in the ultra high vacuum range, b) bringing the substrate to an elevated temperature, and c) flowing, over said substrate, a halogen-free precursor gas of molecules comprising the semiconductor material. Typically, the metal structure characterized by feature dimensions of less than 2.0 microns. Preferably, the metal is tungsten, the semiconductor material is silicon and the gas comprises a silane of the form SinH(2n+2), where n is a positive integer.

摘要翻译： 公开了一种用于在半导体衬底的表面上形成半导体材料外延层的方法，该金属结构设置在金属结构的表面上，该金属的特征在于用于形成金属和半导体材料的化合物的负的吉布斯自由能。 该方法包括以下步骤：a）将基板放置在基本压力在超高真空范围内的反应器容器中，b）使基板升高温度，和c）在所述基板上流过无卤素 包含半导体材料的分子的前体气体。 通常，特征尺寸小于2.0微米的金属结构。 优选地，金属是钨，半导体材料是硅，气体包括形式为SinH（2n + 2）的硅烷，其中n是正整数。

公开(公告)号：US06770500B2

公开(公告)日：2004-08-03

申请号：US10099004

申请日：2002-03-15

申请人： Alessandro Cesare Callegari ,  Christopher P. D'emic ,  Hyungjun Kim ,  Fenton Read McFeely ,  Vijay Narayanan ,  John Jacob Yurkas

发明人： Alessandro Cesare Callegari ,  Christopher P. D'emic ,  Hyungjun Kim ,  Fenton Read McFeely ,  Vijay Narayanan ,  John Jacob Yurkas

IPC分类号： H01L2100

CPC分类号： H01L21/823828 ,  H01L21/28079 ,  H01L21/3003

摘要： A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250° C. and about 500° C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.

摘要翻译： 钝化金属门控CMOS结构的方法，其中金属门控CMOS结构在分子氢气氛中在约250℃至约500℃的温度和至少约200℃的压力下钝化 托尔 本方法提供比通过现有技术的钝化工艺可获得的更低的界面状态密度。

公开(公告)号：US20110052797A1

公开(公告)日：2011-03-03

申请号：US12548269

申请日：2009-08-26

申请人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jacob Yurkas

发明人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jacob Yurkas

IPC分类号： B05D5/12

CPC分类号： C23C8/24 ,  C23C8/80

摘要： Techniques for nitridation of copper (Cu) wires. In one aspect, a method for nitridation of a Cu wire is provided. The method includes the following step. The Cu wire and trimethylsilylazide (TMSAZ) in a carrier gas are contacted at a temperature, pressure and for a length of time sufficient to form a nitridized layer on one or more surfaces of the Cu wire. The Cu wire can be part of a wiring structure and can be embedded in a dielectric media. The dielectric media can comprise an ultra low-k dielectric media.

摘要翻译： 铜（Cu）线的氮化技术。 在一方面，提供了一种用于氮化Cu丝的方法。 该方法包括以下步骤。 载气中的Cu线和三甲基甲硅烷基叠氮化物（TMSAZ）在足以在Cu线的一个或多个表面上形成氮化层的温度和压力下接触。 Cu线可以是布线结构的一部分，并且可以嵌入介电介质中。 电介质介质可以包括超低k电介质介质。

公开(公告)号：US07172968B2

公开(公告)日：2007-02-06

申请号：US10188686

申请日：2002-07-03

申请人： Stephan Alan Cohen ,  Fenton Read McFeely ,  Cevdet Ismail Noyan ,  Kenneth Parker Rodbell ,  Robert Rosenberg ,  John Jacob Yurkas

发明人： Stephan Alan Cohen ,  Fenton Read McFeely ,  Cevdet Ismail Noyan ,  Kenneth Parker Rodbell ,  Robert Rosenberg ,  John Jacob Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L21/7687 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.

摘要翻译： 本发明涉及用作互补结构例如沟槽电容器或镶嵌布线层作为扩散阻挡层的α-W层。 α-W层是通过使用六羰基钨（W（CO）6）6作为源材料的低温/压力化学气相沉积方法形成的单相材料。

公开(公告)号：US6091122A

公开(公告)日：2000-07-18

申请号：US21262

申请日：1998-02-10

申请人： Douglas Andrew Buchanan ,  Fenton Read McFeely ,  John Jacob Yurkas

发明人： Douglas Andrew Buchanan ,  Fenton Read McFeely ,  John Jacob Yurkas

IPC分类号： H01L29/78 ,  C23C16/16 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： C23C16/16 ,  H01L21/28079 ,  H01L21/32051

摘要： A method of fabricating a mid-gap workfunction tungsten gate or W electrode directly onto a gate dielectric material for use in high speed/high density advanced MOS and CMOS devices is provided which utilizes low temperature/low pressure CVD of a tungsten carbonyl. MOS and CMOS devices containing one or more of the CVD W gates or W electrodes manufactured by the present invention are also provided herein.

摘要翻译： 提供了一种将半间隙功函数钨栅极或W电极直接制造在用于高速/高密度先进MOS和CMOS器件的栅极电介质材料上的方法，该方法利用钨酸低温/低压CVD。 本文还提供了包含由本发明制造的一个或多个CVD W栅极或W电极的MOS器件和CMOS器件。

公开(公告)号：US07037834B2

公开(公告)日：2006-05-02

申请号：US10851384

申请日：2004-05-22

申请人： Fenton Read McFeely ,  John Jacob Yurkas ,  Sandra Malhotra ,  Andrew Simon

发明人： Fenton Read McFeely ,  John Jacob Yurkas ,  Sandra Malhotra ,  Andrew Simon

IPC分类号： H01L21/44

CPC分类号： C23C16/4404 ,  C30B35/00 ,  H01L21/28556

摘要： A deposition member adapted for discharging a deposition material during a deposition process can acquire a coating during the deposition. Such an initial emissivity value is selected for the deposition member, before any of the coating became deposited, that the emissivity of the deposition member remains substantially unchanged during the deposition process. In a representative embodiment the deposition member is coated with an appropriate thin layer for achieving the selected emissivity value.

摘要翻译： 适于在沉积过程中排出沉积材料的沉积构件可以在沉积期间获得涂层。 在任何涂层沉积之前，沉积构件选择这种初始发射率值，沉积构件的发射率在沉积过程中保持基本不变。 在代表性的实施例中，沉积构件涂覆有适当的薄层以实现所选择的发射率值。

公开(公告)号：US06756651B2

公开(公告)日：2004-06-29

申请号：US09963194

申请日：2001-09-26

申请人： Ferenc M. Bozso ,  Fenton Read McFeely ,  John Jacob Yurkas

发明人： Ferenc M. Bozso ,  Fenton Read McFeely ,  John Jacob Yurkas

IPC分类号： H01L2714

CPC分类号： H01L31/1085 ,  H01L31/1133

摘要： A novel photodetector CMOS-compatible photodetector is disclosed in which photo-generation of carriers (electrons) is carried out in the metal of the electrodes, rather than as electron-hole pairs in the semiconductor on which the metal electrodes are deposited. The novel photo detector comprises a silicon or other semiconductor substrate material characterized by an electron energy bandgap, and a pair of metal electrodes disposed upon a surface of the silicon to define therebetween a border area of the surface. One of the two electrodes being exposed to the incident radiation and covering an area of said surface which is larger than the aforesaid border area, the aforesaid metal of the electrodes being characterized by a Fermi level which is within said electron energy bandgap.

摘要翻译： 公开了一种新颖的光电检测器CMOS兼容光电检测器，其中在电极的金属中进行载流子（电子）的光生成，而不是沉积金属电极的半导体中的电子 - 空穴对。 新型光电检测器包括以电子能带隙为特征的硅或其它半导体衬底材料，以及设置在硅表面上的一对金属电极，以在其间界定表面的边界区域。 两个电极中的一个暴露于入射辐射并且覆盖所述表面的大于上述边界区域的区域，上述电极的金属的特征在于在所述电子能带隙内的费米能级。

公开(公告)号：US6017401A

公开(公告)日：2000-01-25

申请号：US170622

申请日：1998-10-13

申请人： Fenton Read McFeely ,  Ismail Cevdet Noyan ,  John Jacob Yurkas

发明人： Fenton Read McFeely ,  Ismail Cevdet Noyan ,  John Jacob Yurkas

IPC分类号： H01L21/22 ,  C23C10/06 ,  C23C14/58 ,  C23C8/06

CPC分类号： C23C14/5846 ,  C23C10/06 ,  C23C14/58 ,  Y10T428/1284

摘要： A method of increasing conductivity of a refractory metal film disposed upon a substrate includes exposing the refractory metal film to an atmosphere comprising a silane of the form Si.sub.n H.sub.(2n+2), where n is a positive integer, while subjecting the refractory metal film to a temperature in excess of 700 degrees Celsius and to a base pressure not exceeding 10.sup.-8 torr for a time period which is chosen to be sufficiently long to increase the conductivity of the refractory metal film to a correspondingly sufficient degree.

摘要翻译： 提高设置在基板上的难熔金属膜的导电性的方法包括将难熔金属膜暴露于含有SiH（2n + 2）形式的硅烷的气氛中，其中n为正整数，同时使难熔金属膜 超过700摄氏度的温度和不超过10-8托的基础压力，该时间段被选择为足够长以将耐火金属膜的导电性提高到相应的足够程度。