公开(公告)号：US06660330B2

公开(公告)日：2003-12-09

申请号：US09829648

申请日：2001-04-10

申请人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

发明人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

IPC分类号： C23C1606

CPC分类号： C23C16/466 ,  C23C16/481 ,  H01L21/28556 ,  H01L21/67109

摘要： The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.

摘要翻译： 本发明涉及一种在基板表面上的金属膜的低压化学气相沉积（CVD）期间确保变形耐受基板的均匀可重复加热的方法和装置。 在本发明中通过将衬底定位在位于CVD反应器室中的加热元件上方的倒角环的斜面上来实现衬底的均匀和可再现的加热。 加热元件，倒角环和衬底底面之间的空间限定了衬底和加热元件之间的空腔，确保衬底被辐射装置加热而不是直接接触。

公开(公告)号：US06380075B1

公开(公告)日：2002-04-30

申请号：US09676546

申请日：2000-09-29

申请人： Cyril Cabral, Jr. ,  Chao-Kun Hu ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon

发明人： Cyril Cabral, Jr. ,  Chao-Kun Hu ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871

摘要： A method for forming an open-bottom liner for a conductor in an electronic structure and devices formed are disclosed. In the method, a pre-processed electronic substrate that has a dielectric layer on top is first provided. Via openings are then formed in a dielectric layer to expose an underlying conductive layer. The electronic substrate is then positioned in a cold-wall, low pressure chemical vapor deposition chamber, while the substrate is heated to a temperature of at least 350° C. A precursor gas is then flowed into the CVD chamber to a partial pressure of not higher than 10 mTorr, and metal is deposited from the precursor gas onto sidewalls of the via openings while bottoms of the via openings are substantially uncovered by the metal. The present invention method may be further enhanced by, optionally, modifications of a I-PVD technique or a seed layer deposition technique.

摘要翻译： 公开了一种用于形成电子结构中的导体的开口底部衬垫和形成的器件的方法。 在该方法中，首先提供在顶部具有电介质层的预处理电子基板。 然后在电介质层中形成通孔以暴露下面的导电层。 然后将电子基板定位在冷壁低压化学气相沉积室中，同时将基板加热至至少350℃的温度。然后将前体气体流入CVD室至不分压 高于10mTorr，并且金属从前体气体沉积到通孔开口的侧壁上，而通路孔的底部基本上不被金属覆盖。 本发明的方法可以通过任选地修饰I-PVD技术或种子层沉积技术进一步增强。

公开(公告)号：US07241696B2

公开(公告)日：2007-07-10

申请号：US10318606

申请日：2002-12-11

申请人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

发明人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：US06661097B1

公开(公告)日：2003-12-09

申请号：US10287155

申请日：2002-11-01

申请人： Larry Clevenger ,  Stanley J. Klepeis ,  Hsiao-Ling Lu ,  Jeffrey R. Marino ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Kwong Hon Wong ,  Chih-Chao Yang

发明人： Larry Clevenger ,  Stanley J. Klepeis ,  Hsiao-Ling Lu ,  Jeffrey R. Marino ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.

摘要翻译： 在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。 用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。 通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

公开(公告)号：US20090151981A1

公开(公告)日：2009-06-18

申请号：US12190814

申请日：2008-08-13

申请人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

IPC分类号： H01B5/14

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中

公开(公告)号：US07446036B1

公开(公告)日：2008-11-04

申请号：US11958691

申请日：2007-12-18

申请人： Tibor Bolom ,  Stephan Grunow ,  David Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David Rath ,  Andrew Herbert Simon

IPC分类号： H01L21/4763 ,  H01L21/461

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中。

公开(公告)号：US06176931B1

公开(公告)日：2001-01-23

申请号：US09430829

申请日：1999-10-29

申请人： Darryl D. Restaino ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon ,  Pavel Smetana ,  Edward C. Cooney, III

发明人： Darryl D. Restaino ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon ,  Pavel Smetana ,  Edward C. Cooney, III

IPC分类号： C23C1600

CPC分类号： C23C14/541 ,  C23C14/50

摘要： Improvements are described for a wafer clamp ring used in an IPVD apparatus to provide cooling for the wafer clamp ring, to protect the wafer clamp ring from ion bombardment, and to prevent damage to the wafer. The wafer clamp ring is placed on a cooling fixture when not required for a deposition process. The fixture is annular in shape and in close thermal contact with a circulating coolant and is thereby cooled below ambient temperature. The cooling line and the cooling fixture are fixed relative to the IPVD device, so that problems associated with flexible cooling lines are avoided. An annular grounded shield may be provided between the plasma and clamp ring to protect the clamp ring against ion bombardment during the deposition process. The wafer clamp ring may have a portion which overhangs the wafer during a deposition process, and which has a ridge portion extending downwards therefrom and tapering to a knife edge. The wafer clamp ring may be fabricated as a split ring with an insulating portion, to prevent heating by induced current in the clamp ring.

摘要翻译： 描述了用于IPVD装置中的晶片夹环的改进，以为晶片夹环提供冷却，以保护晶片夹环避免离子轰击，并防止损坏晶片。 当不需要沉积工艺时，将晶片夹环放置在冷却夹具上。 固定装置的形状为环形，与循环的冷却剂紧密的热接触，从而被冷却到环境温度以下。 冷却管路和冷却固定装置相对于IPVD装置固定，从而避免与柔性冷却管线相关的问题。 可以在等离子体和夹环之间设置环形接地屏蔽件，以在沉积过程中保护夹环免受离子轰击。 晶片夹环可以具有在沉积工艺期间悬垂于晶片的部分，并且具有从其向下延伸并逐渐变细到刀刃的脊部分。 晶片夹环可以制造成具有绝缘部分的开口环，以防止夹紧环中的感应电流加热。

公开(公告)号：US06238532B1

公开(公告)日：2001-05-29

申请号：US09430831

申请日：1999-10-29

申请人： Stephen Mark Rossnagel ,  Darryl D. Restaino ,  Andrew Herbert Simon ,  Pavel Smetana

发明人： Stephen Mark Rossnagel ,  Darryl D. Restaino ,  Andrew Herbert Simon ,  Pavel Smetana

IPC分类号： C23C1440

CPC分类号： H01J37/321 ,  C23C14/32 ,  C23C14/3471

摘要： A cooling structure and a reinforcing structure are described for use with a radio-frequency coil in an ionized physical vapor deposition apparatus. The cooling structure includes a portion for carrying coolant and is proximate to the RF coil along the outer circumference thereof. The cooling structure is shaped relative to the RF coil so that thermal expansion of the RF coil brings the RF coil into close contact with the cooling structure, thereby facilitating heat transfer from the RF coil to the coolant. The reinforcing structure is similarly shaped, and may be integrated with the cooling structure. In addition, the RF coil or cooling/reinforcing structure may be mounted to the wall of the process chamber with telescoping mounting posts, which permit the RF coil to maintain its shape while undergoing thermal expansion. The parasitic inductance of the RF coil leads is reduced by arranging those leads coaxially, thereby minimizing power losses in the RF coil.

摘要翻译： 描述了用于电离物理气相沉积设备中的射频线圈的冷却结构和加强结构。 冷却结构包括用于承载冷却剂并且沿着其外圆周靠近RF线圈的部分。 冷却结构相对于RF线圈成形，使得RF线圈的热膨胀使RF线圈与冷却结构紧密接触，从而有助于从RF线圈到冷却剂的热传递。 加强结构类似地成形，并且可以与冷却结构集成。 此外，RF线圈或冷却/加强结构可以用伸缩式安装柱安装到处理室的壁上，这允许RF线圈在经历热膨胀的同时保持其形状。 RF线圈引线的寄生电感通过将这些引线同轴布置而减小，从而使RF线圈中的功率损耗最小化。

公开(公告)号：US07985928B2

公开(公告)日：2011-07-26

申请号：US12190814

申请日：2008-08-13

申请人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

IPC分类号： H05K1/11

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中。

公开(公告)号：US06949461B2

公开(公告)日：2005-09-27

申请号：US10318605

申请日：2002-12-11

申请人： Sandra G. Malhotra ,  Andrew Herbert Simon

发明人： Sandra G. Malhotra ,  Andrew Herbert Simon

IPC分类号： H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被介电层覆盖。 图案化电介质层以暴露金属导体。 然后将衬垫层沉积到图案中。 然后对衬垫层进行氩溅射蚀刻以去除衬里层并暴露金属导体。 在氩溅射蚀刻的过程中，衬里层被再沉积到图案的侧壁上。 最后，附加层沉积到图案中并覆盖再沉积的衬里层。