公开(公告)号：US06747472B2

公开(公告)日：2004-06-08

申请号：US10052619

申请日：2002-01-18

申请人： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： G01R3126

CPC分类号： H01L24/11 ,  G01R1/0416 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/325 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.

摘要翻译： 一种用于通过将装置芯片临时附接到具有多个具有微树突状特征的容器的载体来测试装置芯片集合的系统; 所述插座与所述器件芯片上的匹配的接触焊盘组匹配并且与所述插座接触; 所述载体另外具有通过互连布线连接到插座的测试垫。 该系统允许将芯片连接在一起，并通过探测载体上的测试垫来整体测试集合。 芯片集合的老化也可以在临时载体上执行，这是可重复使用的。

公开(公告)号：US06275051B1

公开(公告)日：2001-08-14

申请号：US09240121

申请日：1999-01-29

申请人： Thomas W. Bachelder ,  Dennis R. Barringer ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Paul M. Gaschke ,  Mark R. Laforce ,  Charles H. Perry ,  Roger R. Schmidt ,  Joseph J. Van Horn ,  Wade H. White

发明人： Thomas W. Bachelder ,  Dennis R. Barringer ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Paul M. Gaschke ,  Mark R. Laforce ,  Charles H. Perry ,  Roger R. Schmidt ,  Joseph J. Van Horn ,  Wade H. White

IPC分类号： G01R1073

CPC分类号： G01R31/2863

摘要： An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

摘要翻译： 用于在产品晶片上同时测试或燃烧大量集成电路芯片的装置包括安装在第一板上的探针和安装在第二板上的测试器芯片，连接两个板的电连接器。 测试器芯片用于向产品芯片分配电力或用于测试产品芯片。 其所附接的探针和薄膜布线被个性化以用于被探测的特定晶片的焊盘覆盖区。 第一板和第二板的基座对于产品系列中的所有晶片都保持不变。 使用两个电路板提供了测试器芯片在燃烧期间保持在比产品芯片基本上更低的温度，以延长测试器芯片的寿命。 间隙可以用作板之间的绝热，并将间隙密封并抽真空以进行进一步的隔热。 疏散还提供大气压力增加的接触，用于连接板和与晶片的接触。 用于平行测试芯片的探针被布置成月牙形条纹，以便与布置在区域阵列中的探针相比显着增加测试仪的吞吐量。

公开(公告)号：US5519193A

公开(公告)日：1996-05-21

申请号：US966960

申请日：1992-10-27

申请人： Peter E. Freiermuth ,  Kathleen S. Ginn ,  Jeffrey A. Haley ,  Susan J. Lamaire ,  David A. Lewis ,  Gavin T. Mills ,  Timothy A. Redmond ,  Yuk L. Tsang ,  Joseph J. Van Horn ,  Alfred Viehbeck ,  George F. Walker ,  Jer-Ming Yang ,  Clarence S. Long

发明人： Peter E. Freiermuth ,  Kathleen S. Ginn ,  Jeffrey A. Haley ,  Susan J. Lamaire ,  David A. Lewis ,  Gavin T. Mills ,  Timothy A. Redmond ,  Yuk L. Tsang ,  Joseph J. Van Horn ,  Alfred Viehbeck ,  George F. Walker ,  Jer-Ming Yang ,  Clarence S. Long

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/311 ,  H01L21/265 ,  H01L21/268 ,  H01L21/326 ,  H01L21/329 ,  H05B6/80

CPC分类号： G01R31/2881 ,  G01R31/311 ,  Y10S148/071

摘要： The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.

摘要翻译： 所描述的发明涉及在半导体芯片单独和晶圆级别的烧结，电应力，热应力和减少整流结漏电流的微波方法，以及对半导体芯片封装衬底的燃烧和应力的组合 安装在半导体芯片封装基板上的半导体芯片。 微波老化装置在比传统的老化技术更短的时间内，并且避免了对于常规应力和老化技术所要求的特殊工件支架的需要。 此外，描述了微波方法，用于减少重新连接的漏电流，例如半导体器件在完全处理的半导体芯片和晶片上的PN结和肖特基势垒二极管接头。