公开(公告)号：US06747472B2

公开(公告)日：2004-06-08

申请号：US10052619

申请日：2002-01-18

申请人： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： G01R3126

CPC分类号： H01L24/11 ,  G01R1/0416 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/325 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.

摘要翻译： 一种用于通过将装置芯片临时附接到具有多个具有微树突状特征的容器的载体来测试装置芯片集合的系统; 所述插座与所述器件芯片上的匹配的接触焊盘组匹配并且与所述插座接触; 所述载体另外具有通过互连布线连接到插座的测试垫。 该系统允许将芯片连接在一起，并通过探测载体上的测试垫来整体测试集合。 芯片集合的老化也可以在临时载体上执行，这是可重复使用的。

公开(公告)号：US06819000B2

公开(公告)日：2004-11-16

申请号：US10692065

申请日：2003-10-23

申请人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/67144 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00

摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

摘要翻译： 教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。 载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片采用微连接焊盘阵列，其包括粘附层，阻挡层和易熔焊料层，焊盘位于相对于阻挡插座的匹配位置; 器件芯片通过微接点阵列连接到载体，导致能够具有非常高的输入/输出密度和芯片间布线密度的互连。

公开(公告)号：US06661098B2

公开(公告)日：2003-12-09

申请号：US10052620

申请日：2002-01-18

申请人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/67144 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00

摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

摘要翻译： 教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。 载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片的阵列包括粘附层，阻挡层和易熔焊料层的微接合焊盘阵列，焊盘位于相对于屏障插座的匹配位置; 所述器件芯片通过微接点阵列连接到所述载体，导致能够实现非常高的输入/输出密度和芯片间布线密度的互连。

公开(公告)号：US06732908B2

公开(公告)日：2004-05-11

申请号：US10052591

申请日：2002-01-18

申请人： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： B23K3102

CPC分类号： H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.

摘要翻译： 一个微型接头互连结构，包括具有精确可控高度的密集阵列的金属螺柱，并具有接合冶金。 该阵列在要连接到载体的装置芯片上或与其他装置一起在载体上产生，其中一些装置芯片可被选择为具有相似的互连结构，以便将组装的载体形成为一体， 完整的计算，通信或网络系统。

公开(公告)号：US07273804B2

公开(公告)日：2007-09-25

申请号：US11030496

申请日：2005-01-06

申请人： David Angell ,  Frederic Beaulieu ,  Takashi Hisada ,  Adreanne Kelly ,  Samuel Roy McKnight ,  Hiromitsu Miyai ,  Kevin Shawn Petrarca ,  Wolfgang Sauter ,  Richard Paul Volant ,  Caitlin W. Weinstein

发明人： David Angell ,  Frederic Beaulieu ,  Takashi Hisada ,  Adreanne Kelly ,  Samuel Roy McKnight ,  Hiromitsu Miyai ,  Kevin Shawn Petrarca ,  Wolfgang Sauter ,  Richard Paul Volant ,  Caitlin W. Weinstein

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L31/00 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

摘要翻译： 公开了一种具有非平面电介质结构和在非平面电介质结构上共形形成的金属接合层的增强接合焊盘结构。 非平面电介质结构基本上在金属接合层中再现，从而形成非平面金属结构。 围绕非平面金属结构的每一个是介电材料环，其在接合焊盘探测期间提供硬停止，以限制在探测期间可以去除的接合焊盘的量。

公开(公告)号：US06864578B2

公开(公告)日：2005-03-08

申请号：US10249381

申请日：2003-04-03

申请人： David Angell ,  Frederic Beaulieu ,  Takashi Hisada ,  Adreanne Kelly ,  Samuel Roy McKnight ,  Hiromitsu Miyai ,  Kevin Shawn Petrarca ,  Wolfgang Sauter ,  Richard Paul Volant ,  Caitlin W. Weinstein

发明人： David Angell ,  Frederic Beaulieu ,  Takashi Hisada ,  Adreanne Kelly ,  Samuel Roy McKnight ,  Hiromitsu Miyai ,  Kevin Shawn Petrarca ,  Wolfgang Sauter ,  Richard Paul Volant ,  Caitlin W. Weinstein

IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

公开(公告)号：US07855137B2

公开(公告)日：2010-12-21

申请号：US12190173

申请日：2008-08-12

申请人： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

发明人： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L21/76852 ,  H01L21/76885 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

摘要翻译： 在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。 只有导电柱的一面被电镀。 导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。 还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。

公开(公告)号：US07833893B2

公开(公告)日：2010-11-16

申请号：US11775257

申请日：2007-07-10

申请人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

发明人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76873 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76865

摘要： A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

摘要翻译： 形成导线方法的方法。 该方法包括在电介质层上形成电介质硬掩模层; 在介电硬掩模层上形成导电硬掩模层; 形成延伸穿过所述导电和介电硬掩模层的沟槽进入所述电介质层; 在导电硬掩模层和沟槽的侧壁和底部上沉积衬里/籽晶层; 用填充材料填充沟槽; 从所述导电硬掩模层的顶表面去除所述衬里/籽晶层; 从沟槽中移除填充材料; 将金属层电镀到导电硬掩模层和衬里/籽晶层的暴露表面上; 并且从电介质硬掩模层去除金属层和导电硬掩模层，使得金属层和衬里/籽晶层的边缘与电介质硬掩模层的顶表面共面。

公开(公告)号：US20090017616A1

公开(公告)日：2009-01-15

申请号：US11775257

申请日：2007-07-10

申请人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

发明人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76873 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76865

摘要： A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

摘要翻译： 形成导线方法的方法。 该方法包括在电介质层上形成电介质硬掩模层; 在介电硬掩模层上形成导电硬掩模层; 形成延伸穿过所述导电和介电硬掩模层的沟槽进入所述电介质层; 在导电硬掩模层和沟槽的侧壁和底部上沉积衬里/籽晶层; 用填充材料填充沟槽; 从所述导电硬掩模层的顶表面去除所述衬里/籽晶层; 从沟槽中移除填充材料; 将金属层电镀到导电硬掩模层和衬里/籽晶层的暴露表面上; 并且从电介质硬掩模层去除金属层和导电硬掩模层，使得金属层和衬里/籽晶层的边缘与电介质硬掩模层的顶表面共面。

公开(公告)号：US20100038777A1

公开(公告)日：2010-02-18

申请号：US12190173

申请日：2008-08-12

申请人： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

发明人： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L21/76852 ,  H01L21/76885 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

摘要翻译： 在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。 只有导电柱的一面被电镀。 导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。 还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。