公开(公告)号：US6008107A

公开(公告)日：1999-12-28

申请号：US899394

申请日：1997-07-23

申请人： John M. Pierce ,  Sung Tae Ahn

发明人： John M. Pierce ,  Sung Tae Ahn

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  Y10S438/959

摘要： An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

摘要翻译： 通过首先在晶片的表面上形成停止层，在半导体晶片上制造集成电路器件。 孔通过停止层形成，并且阱形成在开口下方的半导体晶片的半导体材料中。 在装置的表面上形成介电层，其基本上填充阱并覆盖停止层。 然后将电介质层平坦化至基本上停止层的水平。 在阻挡层和半导体器件的表面之间设置PAD氧化物层。 将孔和植入物的常规薄膜氧化进入孔的侧壁进行。 使用研磨机械抛光机进行平面化处理，其中机械抛光机当遇到停止层时具有自停特征。

公开(公告)号：US5287663A

公开(公告)日：1994-02-22

申请号：US874823

申请日：1992-04-28

申请人： John M. Pierce ,  Peter H. Renteln

发明人： John M. Pierce ,  Peter H. Renteln

IPC分类号： B24B13/01 ,  B24B37/22 ,  B24D11/00

CPC分类号： B24B37/22

摘要： A polishing pad and a method for polishing semiconductor wafers. The polishing pad includes a polishing layer and a rigid layer. The rigid layer adjacent the polishing layer imparts a controlled rigidity to the polishing layer. The resilient layer adjacent the rigid layer provides substantially uniform pressure to the rigid layer. During operation, the rigid layer and the resilient layer apply an elastic flexure pressure to the polishing layer to induce a controlled flex in the polishing layer to conform to the global topography of the wafer surface while maintaining a controlled rigidity over the local topography of the wafer surface.

摘要翻译： 抛光垫和抛光半导体晶片的方法。 抛光垫包括抛光层和刚性层。 与抛光层相邻的刚性层赋予抛光层刚性。 邻近刚性层的弹性层向刚性层提供基本均匀的压力。 在操作期间，刚性层和弹性层向抛光层施加弹性弯曲压力，以在抛光层中引起受控的弯曲以符合晶片表面的全局形貌，同时保持对晶片的局部形貌的受控刚度 表面。

公开(公告)号：US06948645B2

公开(公告)日：2005-09-27

申请号：US10844820

申请日：2004-05-13

申请人： John M. Pierce ,  Bill Snowa ,  Billie M. Bloodworth

发明人： John M. Pierce ,  Bill Snowa ,  Billie M. Bloodworth

IPC分类号： B60R9/06 ,  B60R11/00 ,  B60R11/06

CPC分类号： B60R11/06

摘要： An adjustable frame, mountable on a vehicle, for releasably securing hand trucks of different sizes and configurations includes: a support platform for receiving a base of a hand truck; a first and a second side member affixed to the platform; a first bracket and a second bracket attached to the first and second side members, respectively, the brackets extending in parallel therewith; an elongate swing bar pivotally connected to the first bracket and pivotal between a first position that retains the hand truck on the platform, and a second position, which allows access and removal of the hand truck from the platform; and a latch mounted on the swing bar. The second bracket may include a strike that engages the latch for releasably securing the swing bar in the first position. Cushioned crossbars attachable to the side members dampen vibration of the hand truck during transportation.

摘要翻译： 可安装在车辆上的可调节框架，用于可释放地固定不同尺寸和构型的手推车，包括：用于接收手推车底座的支撑平台; 固定在平台上的第一和第二侧部件; 分别附接到第一和第二侧构件的第一支架和第二支架，支架与其平行地延伸; 一个可摆动地连接到第一支架并在将手推车保持在平台上的第一位置之间枢转的细长摆动杆和允许从平台接近和移除手推车的第二位置; 以及安装在摆动杆上的闩锁。 第二支架可以包括接合闩锁的撞击件，用于可释放地将摆杆固定在第一位置。 附着在侧面构件上的缓冲式横梁在运输过程中减轻了手推车的振动。

公开(公告)号：US4267012A

公开(公告)日：1981-05-12

申请号：US34781

申请日：1979-04-30

申请人： John M. Pierce ,  William I. Lehrer ,  Kenneth J. Radigan

发明人： John M. Pierce ,  William I. Lehrer ,  Kenneth J. Radigan

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/283

CPC分类号： H01L21/32137 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/32134 ,  H01L21/32136

摘要： A process for patterning regions on a semiconductor structure comprises the steps of forming a first layer of an alloy of tungsten and titanium on the semiconductor structure, forming a conductive layer of aluminum or chemically similar material on the surface of the tungsten-titanium alloy, removing the undesired portions of the conductive layer by etching with a plasma and removing the thereby exposed portions of the tungsten-titanium alloy layer by chemical etching.

摘要翻译： 用于图案化半导体结构上的区域的工艺包括以下步骤：在半导体结构上形成钨和钛合金的第一层，在钨钛合金的表面上形成铝或化学相似材料的导电层，去除 通过用等离子体蚀刻并通过化学蚀刻去除钨 - 钛合金层的暴露部分来导致导电层的不希望的部分。

公开(公告)号：US06406093B1

公开(公告)日：2002-06-18

申请号：US09537612

申请日：2000-03-29

申请人： Ronald L. Miotto ,  Kenneth R. Parrish ,  John M. Pierce ,  David R. Fabry ,  Benedict J. Messina ,  Cathy A. Sadler

发明人： Ronald L. Miotto ,  Kenneth R. Parrish ,  John M. Pierce ,  David R. Fabry ,  Benedict J. Messina ,  Cathy A. Sadler

IPC分类号： A47C3102

CPC分类号： B60N2/5825

摘要： A seat assembly includes a seat structural member and a clip having first and second hook portions. The first hook portion of the clip is attached to the structural member. The seat assembly also includes a first trim material having an edge attached to the clip. Preferably, the first trim material is an elastomeric material. The seat assembly further includes a second trim material having a first edge attached to the first trim material and a second edge attached to the second hook portion.

摘要翻译： 座椅组件包括座椅结构构件和具有第一和第二钩部分的夹子。 夹子的第一钩部附接到结构构件。 座椅组件还包括具有附接到夹子的边缘的第一装饰材料。 优选地，第一装饰材料是弹性体材料。 座椅组件还包括第二装饰材料，其具有附接到第一装饰材料的第一边缘和附接到第二钩部分的第二边缘。

公开(公告)号：US5422289A

公开(公告)日：1995-06-06

申请号：US874675

申请日：1992-04-27

申请人： John M. Pierce

发明人： John M. Pierce

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/28123 ,  H01L21/3212 ,  H01L29/41783 ,  H01L29/66628

摘要： A method is disclosed for forming MOSFET devices on a semiconductor substrate including steps of depositing layers of polysilicon, dielectric, and polysilicon again. Each polysilicon layer is planarized after it is deposited. The dielectric layer is patterned and etched to delineate active regions and interconnect grooves. After the second polysilicon layer is planarized, the material in the active region is patterned and etched to form a gate and source and drain areas. The appropriate areas of the active region are doped as necessary to form the source and drain.

摘要翻译： 公开了一种用于在半导体衬底上形成MOSFET器件的方法，包括再次沉积多晶硅，电介质和多晶硅层的步骤。 沉积后，每个多晶硅层被平坦化。 对介电层进行图案化和蚀刻以描绘有源区和互连槽。 在第二多晶硅层被平坦化之后，有源区域中的材料被图案化和蚀刻以形成栅极和源极和漏极区域。 必要时掺杂有源区的适当区域以形成源极和漏极。

公开(公告)号：US5094972A

公开(公告)日：1992-03-10

申请号：US538645

申请日：1990-06-14

申请人： John M. Pierce ,  Sung T. Ahn

发明人： John M. Pierce ,  Sung T. Ahn

IPC分类号： H01L21/304 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S438/959

摘要： An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

公开(公告)号：US4630343A

公开(公告)日：1986-12-23

申请号：US773842

申请日：1985-09-06

申请人： John M. Pierce ,  William I. Lehrer

发明人： John M. Pierce ,  William I. Lehrer

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L23/31 ,  H01L21/461

CPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/31604 ,  H01L21/76224 ,  H01L23/3178 ,  H01L2924/0002

摘要： An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

摘要翻译： 集成电路结构包括多个岛状半导体材料（16-1至16-5），每个岛通过围绕所述岛形成为环形的沟槽与相邻的岛分离，以横向限定每个这样的岛的尺寸，氧化物 （13-1至13-6）和所述岛的表面上形成的（12,14）和沉积在所述凹槽中的所述氧化物（14）上并且在所述装置的顶表面上的选定的玻璃（15） 所述玻璃具有其在半导体材料岛的掺杂剂基本上重新分布的温度以下的温度下流动的性质，所述选定的玻璃（15）具有基本上平坦的顶表面，从而使所述结构基本上平坦的顶表面。

公开(公告)号：US4490737A

公开(公告)日：1984-12-25

申请号：US362322

申请日：1982-03-26

申请人： John M. Pierce ,  William I. Lehrer

发明人： John M. Pierce ,  William I. Lehrer

IPC分类号： C03C3/062 ,  C03C3/097 ,  C03C4/16 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H05K1/03 ,  H05K3/28 ,  H01L23/30 ,  H01L29/34 ,  C03C3/04

CPC分类号： H01L23/291 ,  C03C3/062 ,  C03C3/097 ,  C03C4/16 ,  H01L21/316 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/28

摘要： A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

摘要翻译： 用于半导体器件的低温绝缘玻璃包括锗，硅，氧和磷的混合物。 在优选的实施方案中，玻璃包含约40％至55％的二氧化硅（SiO 2），约55％至40％的二氧化锗（GeO 2）和1％至约5％的五氧化二磷（P 2 O 5）的混合物， 按摩尔％计。

公开(公告)号：US4489482A

公开(公告)日：1984-12-25

申请号：US501348

申请日：1983-06-06

申请人： Thomas Keyser ,  Michael E. Thomas ,  John M. Pierce ,  James M. Cleeves

发明人： Thomas Keyser ,  Michael E. Thomas ,  John M. Pierce ,  James M. Cleeves

IPC分类号： H01L23/52 ,  C23F1/00 ,  C23F1/18 ,  C23F1/20 ,  C23F4/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/92 ,  H01L21/285

CPC分类号： C23F1/18 ,  C23F1/20 ,  C23F4/00 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76886

摘要： A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .

摘要翻译： 公开了一种将铜浸入半导体器件中的铝互连线中的方法。 在第一实施例中，通过蚀刻在铝层上形成互连图案，同时铝基本上不含铜，然后将铜引入所形成的互连线。 在第二实施例中，在形成期望的互连图案之前将铜引入铝层。 在蚀刻之前，从要蚀刻的区域去除富铜层。 该方法促进了由于铜的存在而抑制的铝的氯等离子体蚀刻。 该方法对于各种湿法蚀刻工艺也是有用的，其中发现富铜层的形成在后续处理期间使铝层稳定。