公开(公告)号：US08470670B2

公开(公告)日：2013-06-25

申请号：US12565459

申请日：2009-09-23

申请人： John Power ,  Danny Pak-Chum Shum ,  Wolfgang Dickenscheid ,  Robert Strenz

发明人： John Power ,  Danny Pak-Chum Shum ,  Wolfgang Dickenscheid ,  Robert Strenz

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881

摘要： One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.

摘要翻译： 一个或多个实施例可以涉及制造半导体器件的方法，包括：制造半导体器件的方法，包括：提供衬底; 在所述基板上形成电荷存储层; 在所述电荷存储层上形成控制栅极层; 在所述控制栅极层上形成掩模; 使用掩模，蚀刻控制栅极层和电荷存储层; 在蚀刻的控制栅极层和蚀刻的电荷存储层上形成选择栅极层; 在所述选择栅极层上形成附加层; 蚀刻附加层以在选择栅极层上形成侧壁间隔物; 并蚀刻选择栅极层。

公开(公告)号：US20100052178A1

公开(公告)日：2010-03-04

申请号：US12201888

申请日：2008-08-29

申请人： Dirk Meinhold ,  Heinrich Koerner ,  Wolfgang Dickenscheid

发明人： Dirk Meinhold ,  Heinrich Koerner ,  Wolfgang Dickenscheid

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76879 ,  H01L21/768 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

摘要翻译： 一个或多个实施例涉及一种半导体器件，其包括：包括侧壁的导电层; 导电覆盖层，其设置在所述导电层上并且横向延伸超过所述导电层的所述侧壁的横向突出端; 以及与导电覆盖层电接触的导电通孔。

公开(公告)号：US08994179B2

公开(公告)日：2015-03-31

申请号：US12201888

申请日：2008-08-29

申请人： Dirk Meinhold ,  Heinrich Koerner ,  Wolfgang Dickenscheid

发明人： Dirk Meinhold ,  Heinrich Koerner ,  Wolfgang Dickenscheid

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76879 ,  H01L21/768 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

摘要翻译： 一个或多个实施例涉及一种半导体器件，其包括：包括侧壁的导电层; 导电覆盖层，其设置在所述导电层上并且横向延伸超过所述导电层的所述侧壁的横向突出端; 以及与导电覆盖层电接触的导电通孔。

公开(公告)号：US06965809B2

公开(公告)日：2005-11-15

申请号：US10609464

申请日：2003-06-27

申请人： Wolfgang Dickenscheid ,  Frank Meyer ,  Stephanie Delage ,  Götz Springer

发明人： Wolfgang Dickenscheid ,  Frank Meyer ,  Stephanie Delage ,  Götz Springer

IPC分类号： B24B37/04 ,  B24B51/00 ,  H01L21/304 ,  G06F19/00

CPC分类号： B24B51/00 ,  B24B37/042

摘要： A method for characterizing and simulating a CMP process, in which a substrate to be polished, in particular a semiconductor wafer, is pressed onto a polishing cloth and is rotated relative to the latter for a defined polishing time. The method includes defining a set of process parameters, in particular a compressive force and a relative rotational speed between a substrate and polishing cloth; preparing and characterizing a test substrate having test patterns with different structure densities using the defined process parameters; determining a set of model parameters for simulating the CMP process from results of the characterization of the test substrate; determining layout parameters of the substrate which is to be polished; defining a profile of demands for a CMP process result for the substrate to be polished; and simulating the CMP process in order to determine the polishing time required to satisfy the profile of demands.

摘要翻译： 用于表征和模拟CMP工艺的方法，其中要抛光的衬底，特别是半导体晶片被压在抛光布上，并相对于抛光布在相应的抛光时间内旋转。 该方法包括定义一组工艺参数，特别是限定衬底和抛光布之间的压缩力和相对转动速度; 使用所定义的工艺参数来制备和表征具有不同结构密度的测试图案的测试基板; 从测试基板的表征结果确定一组用于模拟CMP工艺的模型参数; 确定待抛光的衬底的布局参数; 定义要抛光的基底的CMP工艺结果的要求的轮廓; 并模拟CMP工艺以确定满足需求曲线所需的抛光时间。

公开(公告)号：US06833324B2

公开(公告)日：2004-12-21

申请号：US10424173

申请日：2003-04-25

申请人： Grit Bonsdorf ,  Wolfgang Dickenscheid

发明人： Grit Bonsdorf ,  Wolfgang Dickenscheid

IPC分类号： H01L21302

CPC分类号： H01L21/67028 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： A surface of a semiconductor wafer is cleaned following a chemical mechanical polishing process. With the semiconductor wafer rotating continuously, an integrated process sequence is used to etch the surface, rinse the surface, and they dry the surface. The apparatus for cleaning the semiconductor wafer has a turntable in a process chamber for rotating the wafer, a feed for cleaning medium, and a return.

摘要翻译： 在化学机械抛光工艺之后，清洁半导体晶片的表面。 在半导体晶片连续旋转的情况下，使用整合的工艺顺序蚀刻表面，冲洗表面，并干燥表面。 用于清洁半导体晶片的装置在用于旋转晶片的处理室中具有转台，用于清洁介质的进给和返回。

公开(公告)号：US6068540A

公开(公告)日：2000-05-30

申请号：US80912

申请日：1998-05-18

申请人： Wolfgang Dickenscheid ,  Goetz Springer

发明人： Wolfgang Dickenscheid ,  Goetz Springer

IPC分类号： B24B49/00 ,  B24D7/12 ,  B24D13/14 ,  B24D7/22

CPC分类号： B24B37/205 ,  B24B49/00

摘要： The polishing device grinds or polishes semiconductor substrates. The device includes a polishing table, into which a measuring device is integrated and a through opening. A polishing cloth covers the polishing table. The polishing cloth has at least one opening formed therein which corresponds to the through opening in the polishing table. The invention also relates to a polishing cloth for use in the polishing device.

摘要翻译： 抛光装置研磨或抛光半导体衬底。 该装置包括一个研磨台，一个测量装置整合到该抛光台中，一个通孔。 抛光布覆盖抛光台。 抛光布具有形成在其中的至少一个开口，其对应于抛光台中的通孔。 本发明还涉及一种用于抛光装置的抛光布。