公开(公告)号：US07657654B2

公开(公告)日：2010-02-02

申请号：US11189584

申请日：2005-07-25

申请人： Earl T. Cohen ,  Ibrahim Delibalta ,  Jonathan Rosen

发明人： Earl T. Cohen ,  Ibrahim Delibalta ,  Jonathan Rosen

IPC分类号： G06F15/173 ,  G06F15/167 ,  G06F9/26

CPC分类号： G06F17/30286 ,  H04L45/745

摘要： A resource unit has a request interface to allow the unit to receive a request and associated data. The resource unit also has a hashing engine to create a hash of the associated data, a modulo engine to create a modulus result, a read engine to perform a memory read, and a results interface to allow the device to return results.

摘要翻译： 资源单元具有允许单元接收请求和关联数据的请求接口。 资源单元还具有哈希引擎来创建关联数据的散列，用于创建模数结果的模引擎，执行存储器读取的读引擎，以及允许设备返回结果的结果接口。

公开(公告)号：US07702855B2

公开(公告)日：2010-04-20

申请号：US11202477

申请日：2005-08-11

申请人： Jonathan Rosen ,  Earl T. Cohen

发明人： Jonathan Rosen ,  Earl T. Cohen

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/30101 ,  G06F9/30134

摘要： A processing device employs a stack memory in a region of an external memory. The processing device has a stack pointer register to store a current top address for the stack memory. One of several techniques is used to determine which portion or portions of the external memory correspond to the stack region. A more efficient memory policy is implemented, whereby pushes to the stack do not have to read data from the external memory in to a cache, and whereby pops from the stack do not cause stale stack data to be written back from the cache to the external memory.

摘要翻译： 处理装置在外部存储器的区域中采用堆栈存储器。 处理装置具有堆栈指针寄存器，用于存储堆栈存储器的当前顶部地址。 使用几种技术之一来确定外部存储器的哪个部分或多个部分对应于堆栈区域。 实现更有效的存储器策略，由此推送到堆栈不必将数据从外部存储器读取到高速缓存中，并且其中来自堆栈的弹出不会使过期堆栈数据从高速缓存写回外部 记忆。

公开(公告)号：US08914696B2

公开(公告)日：2014-12-16

申请号：US13597489

申请日：2012-08-29

申请人： Zhengang Chen ,  Earl T. Cohen

发明人： Zhengang Chen ,  Earl T. Cohen

IPC分类号： G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： G06F11/106

摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters.

摘要翻译： 公开了一种具有第一电路和第二电路的装置。 第一电路可以被配置为（i）在区域的读取擦除期间从存储器电路的区域读取数据，以及（ii）基于（a）数据生成多个统计信息，以及（b）一个或多个位 在数据的错误校正期间执行翻转。 存储器电路通常被配置为将数据存储在非易失性状态中。 可以使用一个或多个参考电压来读取数据。 第二电路可以被配置为（i）基于统计信息来更新区域的多个参数，以及（ii）基于参数计算参考电压的更新值。

公开(公告)号：US08667001B2

公开(公告)日：2014-03-04

申请号：US13528064

申请日：2012-06-20

申请人： Darpan Dinker ,  Andrew David Eckhardt ,  Darryl Manabu Ouye ,  Brian Walter O'Krafka ,  Earl T. Cohen ,  Thomas M. McWilliams

发明人： Darpan Dinker ,  Andrew David Eckhardt ,  Darryl Manabu Ouye ,  Brian Walter O'Krafka ,  Earl T. Cohen ,  Thomas M. McWilliams

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F12/0842 ,  G06F12/0866 ,  G06F17/30575 ,  G06F2212/2022 ,  Y02D10/13

摘要： A distributed database system has multiple compute nodes each running an instance of a database management system (DBMS) program that accesses database records in a local buffer cache. Records are persistently stored in distributed flash memory on multiple storage nodes. A Sharing Data Fabric (SDF) is a middleware layer between the DBMS programs and the storage nodes and has API functions called by the DBMS programs when a requested record is not present in the local buffer cache. The SDF fetches the requested record from flash memory and loads a copy into the local buffer cache. The SDF has threads on a home storage node that locate database records using a node map. A global cache directory locks and pins records to local buffer caches for updating by a node's DBMS program. DBMS operations are grouped into transactions that are committed or aborted together as a unit.

摘要翻译： 分布式数据库系统具有多个计算节点，每个运行节点都运行数据库管理系统（DBMS）程序的实例，该程序访问本地缓冲区高速缓存中的数据库记录。 记录永久存储在多个存储节点上的分布式闪存中。 共享数据结构（SDF）是DBMS程序和存储节点之间的中间件层，当本地缓冲区高速缓存中不存在所请求的记录时，具有由DBMS程序调用的API函数。 SDF从闪存中提取所请求的记录，并将副本加载到本地缓冲区高速缓存中。 SDF在家用存储节点上具有使用节点映射定位数据库记录的线程。 全局缓存目录锁定和引导记录到本地缓冲区高速缓存，以便由节点的DBMS程序进行更新。 DBMS操作被分组为作为一个单元一起提交或中止的事务。

公开(公告)号：US20130297986A1

公开(公告)日：2013-11-07

申请号：US13464433

申请日：2012-05-04

申请人： Earl T. Cohen

发明人： Earl T. Cohen

IPC分类号： G06F12/00 ,  G06F11/10 ,  H03M13/05

CPC分类号： G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0676 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1072 ,  G06F2206/1014 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

摘要： An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

公开(公告)号：US07944930B2

公开(公告)日：2011-05-17

申请号：US11298965

申请日：2005-12-09

申请人： Sha Ma ,  Earl T. Cohen

发明人： Sha Ma ,  Earl T. Cohen

IPC分类号： H04L12/28 ,  H04L12/54

CPC分类号： G06F12/023

摘要： A networking device employing memory buffering in which a first memory is logically configured into blocks, and the blocks are logically configured into particles, where a second memory is configured to mirror the first memory in which a fixed number of bits in the second memory are allocated for each particle in the first memory so that scheduling and datagram lengths of packets stored in the first memory may be stored in the second memory. Other embodiments are described and claimed.

摘要翻译： 一种采用存储器缓冲的网络设备，其中第一存储器在逻辑上被配置成块，并且所述块被逻辑地配置成颗粒，其中第二存储器被配置为镜像其中分配了第二存储器中固定位数的第一存储器 对于第一存储器中的每个粒子，使得存储在第一存储器中的分组的调度和数据报长度可以存储在第二存储器中。 描述和要求保护其他实施例。

公开(公告)号：US20090240869A1

公开(公告)日：2009-09-24

申请号：US12197899

申请日：2008-08-25

申请人： Brian Walter O'Krafka ,  Michael John Koster ,  Darpan Dinker ,  Earl T. Cohen ,  Thomas M. McWilliams

发明人： Brian Walter O'Krafka ,  Michael John Koster ,  Darpan Dinker ,  Earl T. Cohen ,  Thomas M. McWilliams

IPC分类号： G06F12/02 ,  G06F13/00 ,  G06F9/54

CPC分类号： G06F12/0284 ,  G06F12/0806 ,  G06F12/0866 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/2542 ,  Y02D10/13

摘要： A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM.

摘要翻译： 共享数据结构（SDF）使得连接到多个计算节点的闪存看起来是由许多计算节点上运行的许多应用程序全局而共享的单个大内存空间。 存储在家庭节点的闪存中的闪存对象通过在节点上执行的SDF线程在动作节点处复制到DRAM中的对象缓存。 家庭节点具有在家庭节点的闪存中定位闪存对象的闪存对象映射，以及将对象的副本定位在其他共享节点中的全局高速缓存目录。 应用程序使用应用程序编程接口（API）到SDF中透明地获取和放置对象，而不考虑对象在许多计算节点上的位置。 SDF线程和表控制闪存和DRAM中对象的一致性。

公开(公告)号：US07500009B2

公开(公告)日：2009-03-03

申请号：US10777607

申请日：2004-02-11

申请人： Earl T. Cohen ,  Christopher J. Kappler

发明人： Earl T. Cohen ,  Christopher J. Kappler

IPC分类号： G06F15/16

CPC分类号： H04L47/10 ,  H04L47/215 ,  H04L47/22 ,  H04L47/527

摘要： Rate computations are performed such as for use in scheduling activities, such as, but not limited to packets, processes, traffic flow, etc. One implementation identifies an approximated inverse rate, a fix-up adjustment value, and a quantum. An activity measurement value is maintained based on a measure of activity, and a rate control value is maintained based on the measure of activity and the approximated inverse rate. The fix-up adjustment value is applied once each quantum to the rate control value to maintain rate accuracy of the activity. In one implementation, the control value is a scheduling value used for determining when to perform a next part of the activity (e.g., send one or more packets). Scheduling rates are efficiently and compactly stored in an inverse form, which may have advantages in terms of rate granularity, accuracy, and the ability to deliver service smoothly.

摘要翻译： 执行速率计算，例如用于调度活动，例如但不限于分组，进程，业务流程等。一个实现标识近似的反向速率，修正调整值和量子。 基于活动度量维持活动测量值，并且基于活动度量和近似反向率来维持速率控制值。 固定调整值每一个量程应用于速率控制值，以保持活动的速率准确性。 在一个实现中，控制值是用于确定何时执行活动的下一部分（例如，发送一个或多个分组）的调度值。 调度速率以反向形式被有效和紧凑地存储，这可以在速率粒度，准确度和顺利地提供服务的能力方面具有优点。

公开(公告)号：US20090049279A1

公开(公告)日：2009-02-19

申请号：US12102417

申请日：2008-04-14

申请人： Donald E. Steiss ,  Earl T. Cohen ,  John J. Williams

发明人： Donald E. Steiss ,  Earl T. Cohen ,  John J. Williams

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3802

摘要： The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an-instruction fetch sequence responsive to an instruction queue depth on a per thread basis. In a lower pipeline, a thread interleaver determines a thread interleave sequence responsive to thread conditions including thread latency conditions. The thread interleaver selects threads using a two-level round robin arbitration. Thread latency signals are active responsive to thread latencies such as thread stalls, cache misses, and interlocks. During the subsequent one or more clock cycles, the thread is ineligible for arbitration. In one embodiment, other thread conditions affect selection decisions such as local priority, global stalls, and late stalls.

摘要翻译： 本发明提供了一种诸如网络处理器的网络多线程处理器，其包括线程交织器，其执行细粒度线程决定以避免指令执行资源的不充分利用，尽管具有大的通信延迟。 在上部流水线中，指令单元响应于每个线程上的指令队列深度来确定指令获取序列。 在较低流水线中，线程交织器响应于包括线程等待时间条件的线程状况来确定线程交织序列。 线程交织器使用两级循环仲裁来选择线程。 线程延迟信号响应于线程延迟（如线程停止，高速缓存未命中和互锁）而有效。 在随后的一个或多个时钟周期中，线程不符合仲裁规则。 在一个实施例中，其他线程条件影响选择决策，例如本地优先级，全局档位和延迟档。

公开(公告)号：US07043596B2

公开(公告)日：2006-05-09

申请号：US10113060

申请日：2002-03-29

申请人： Thomas M. McWilliams ,  Jeffrey B. Rubin ,  Michael W. Parkin ,  Oyekunle A. Olukotun ,  Derek E. Pappas ,  Jeffrey M. Broughton ,  David R. Emberson ,  David S. Allison ,  Ashley N. Saulsbury ,  Earl T. Cohen ,  Nyles I. Nettleton ,  James B. Burr ,  Liang T. Chen

发明人： Thomas M. McWilliams ,  Jeffrey B. Rubin ,  Michael W. Parkin ,  Oyekunle A. Olukotun ,  Derek E. Pappas ,  Jeffrey M. Broughton ,  David R. Emberson ,  David S. Allison ,  Ashley N. Saulsbury ,  Earl T. Cohen ,  Nyles I. Nettleton ,  James B. Burr ,  Liang T. Chen

IPC分类号： G06F13/00 ,  H04L12/28

CPC分类号： G06F17/5022 ,  G06F15/8023 ,  H04L49/10 ,  H04L49/101

摘要： A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.