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    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    1.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件，包括备用抗体阵列和半导体存储器件的抗体修复方法

    公开(公告)号：US20130003477A1

    公开(公告)日：2013-01-03

    申请号：US13534161

    申请日：2012-06-27

    申请人： Ju-Seop PARK ,  Sin Ho KIM ,  Byung-Sik MOON ,  Jong-Pil SON ,  Jin-Ho KIM ,  Hyoung-Joo KIM ,  Jong-Min OH ,  Seong-Jin JANG

    发明人： Ju-Seop PARK ,  Sin Ho KIM ,  Byung-Sik MOON ,  Jong-Pil SON ,  Jin-Ho KIM ,  Hyoung-Joo KIM ,  Jong-Min OH ,  Seong-Jin JANG

    IPC分类号： G11C11/21 ,  G11C29/44

    CPC分类号： G11C29/027 ,  G11C29/789 ,  G11C29/808

    摘要： A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells.

    摘要翻译： 提供了包括反熔丝电池阵列和备用反熔丝电池阵列的半导体存储器件。 反熔丝电池阵列包括以第一方向布置的第一组反熔丝元件，并且第一组反熔丝电池中的每一个连接到第一至第n个字线中的对应的一个。 备用反熔断电池阵列包括沿第一方向布置的第一备用组反熔丝单元，并且第一备用组反熔丝单元中的每一个连接到第一至第九备用字线中相应的一个。 第一操作控制电路被配置为编制反冒点电池阵列和备用反熔丝电池阵列的反熔丝，并且读取每个反熔丝的状态。 第一操作控制电路通常连接到第一组反熔丝电池和第一备用反熔丝电池组。

    FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    4.
    发明申请
    FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US20120039140A1

    公开(公告)日：2012-02-16

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho KIM ,  Jong-Pil SON ,  Seong-Jin JANG ,  Byung-Sik MOON ,  Seung-Hoon OH ,  Ju-Seop PARK

    发明人： Jin-Ho KIM ,  Jong-Pil SON ,  Seong-Jin JANG ,  Byung-Sik MOON ,  Seung-Hoon OH ,  Ju-Seop PARK

    IPC分类号： G11C29/04 ,  G11C17/16

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME 有权
    半导体存储器件，包括其的存储器系统和校正其中的错误的方法

    公开(公告)号：US20160062830A1

    公开(公告)日：2016-03-03

    申请号：US14729295

    申请日：2015-06-03

    申请人： Sang-Uhn CHA ,  Hoi-Ju CHUNG ,  Jong-Pil SON ,  Kwang-Il PARK ,  Seong-Jin JANG

    发明人： Sang-Uhn CHA ,  Hoi-Ju CHUNG ,  Jong-Pil SON ,  Kwang-Il PARK ,  Seong-Jin JANG

    IPC分类号： G06F11/10 ,  G11C29/52

    CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

    摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

    摘要翻译： 半导体存储器件包括其中布置有多个存储器单元的存储单元阵列。 半导体存储器件包括：纠错码（ECC）电路，被配置为基于主数据产生奇偶校验数据，将包括主数据和奇偶校验数据的码字写入存储单元阵列，将所选择的存储单元行的码字读取到 产生综合征，并且基于每个符号基于综合征来校正读取的码字中的错误。 主数据包括所选存储单元行的第一存储单元的第一数据和所选存储单元行的第二存储单元的第二数据。 将第一数据和第二数据分配给多个符号的一个符号，并且第一存储单元和第二存储单元在存储单元阵列中彼此相邻。

    MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION
    6.
    发明申请
    MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION 有权
    具有错误通知功能的存储器

    公开(公告)号：US20160055056A1

    公开(公告)日：2016-02-25

    申请号：US14729656

    申请日：2015-06-03

    申请人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

    发明人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

    IPC分类号： G06F11/10 ,  G11C29/52

    CPC分类号： G06F11/1008 ,  G06F11/1004 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1666 ,  G11C2029/0411

    摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

    摘要翻译： 具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。 当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

    MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE
    8.
    发明申请
    MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE 有权
    具有选择性错误修正代码的存储器件

    公开(公告)号：US20140013183A1

    公开(公告)日：2014-01-09

    申请号：US13915179

    申请日：2013-06-11

    申请人： Young-Soo SOHN ,  Chul-Woo PARK ,  Jong-Pil SON ,  Jung-bae LEE

    发明人： Young-Soo SOHN ,  Chul-Woo PARK ,  Jong-Pil SON ,  Jung-bae LEE

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1012 ,  G06F11/10 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G11C2029/0411 ,  H03M13/3707

    摘要： An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.

    摘要翻译： 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。