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    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    1.
    发明授权
    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
    防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法

    公开(公告)号：US08514648B2

    公开(公告)日：2013-08-20

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    2.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    Fuse circuit and semiconductor memory device including the same
    5.
    发明授权
    Fuse circuit and semiconductor memory device including the same 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US08599635B2

    公开(公告)日：2013-12-03

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    发明人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

    Semiconductor memory cell array including dummy bit-line and word-line and semiconductor memory device having the same
    9.
    发明授权
    Semiconductor memory cell array including dummy bit-line and word-line and semiconductor memory device having the same 有权
    包括虚拟位线和字线的半导体存储单元阵列和具有其的半导体存储器件

    公开(公告)号：US08514610B2

    公开(公告)日：2013-08-20

    申请号：US13616039

    申请日：2012-09-14

    申请人： Sang-Woong Shin ,  Seong-Jin Jang

    发明人： Sang-Woong Shin ,  Seong-Jin Jang

    IPC分类号： G11C7/02

    CPC分类号： G11C7/02 ,  G11C7/14 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/24

    摘要： A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.

    摘要翻译： 半导体存储单元阵列包括多个位线，多个字线，多个存储单元，多个虚拟存储单元，多个虚拟位线和多个虚拟字线。 虚拟位线位于位线的外部区域。 虚拟字线在字线的外部区域。 虚拟位线保持在浮置状态。 虚拟字线保持关闭电压。

    SEMICONDUCTOR DEVICE, A PARALLEL INTERFACE SYSTEM AND METHODS THEREOF
    10.
    发明申请
    SEMICONDUCTOR DEVICE, A PARALLEL INTERFACE SYSTEM AND METHODS THEREOF 有权
    半导体器件，并行接口系统及其方法

    公开(公告)号：US20130135956A1

    公开(公告)日：2013-05-30

    申请号：US13483719

    申请日：2012-05-30

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    IPC分类号： G11C7/22

    CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

    摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

    摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。