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    Fuse circuit and semiconductor memory device including the same
    1.
    发明授权
    Fuse circuit and semiconductor memory device including the same 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US08599635B2

    公开(公告)日：2013-12-03

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    发明人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

    Semiconductor device including fuse array and method of operation the same
    3.
    发明授权
    Semiconductor device including fuse array and method of operation the same 有权
    包括熔丝阵列的半导体装置及其操作方法相同

    公开(公告)号：US08482989B2

    公开(公告)日：2013-07-09

    申请号：US13295484

    申请日：2011-11-14

    申请人： Jong-pil Son ,  Seong-jin Jang ,  Byung-sik Moon ,  Ju-seop Park

    发明人： Jong-pil Son ,  Seong-jin Jang ,  Byung-sik Moon ,  Ju-seop Park

    IPC分类号： G11C7/00

    CPC分类号： H01L27/101 ,  G11C17/14 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.

    摘要翻译： 提供一种包括熔丝的半导体器件及其操作方法。 半导体器件包括熔丝阵列，第一寄存器单元和第二寄存器单元。 熔丝阵列包括多个行和列。 第一寄存器单元从熔丝阵列接收至少一行熔丝数据。 至少一行熔丝数据的保险丝数据由第一寄存器单元并行接收。 第二寄存器单元从第一寄存器单元一次接收至少一个位的熔丝数据。

    FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    4.
    发明申请
    FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US20120039140A1

    公开(公告)日：2012-02-16

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho KIM ,  Jong-Pil SON ,  Seong-Jin JANG ,  Byung-Sik MOON ,  Seung-Hoon OH ,  Ju-Seop PARK

    发明人： Jin-Ho KIM ,  Jong-Pil SON ,  Seong-Jin JANG ,  Byung-Sik MOON ,  Seung-Hoon OH ,  Ju-Seop PARK

    IPC分类号： G11C29/04 ,  G11C17/16

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

    Image capture device and method of operating the same
    5.
    发明授权
    Image capture device and method of operating the same 有权
    图像捕获装置及其操作方法

    公开(公告)号：US08059175B2

    公开(公告)日：2011-11-15

    申请号：US11979886

    申请日：2007-11-09

    申请人： Ju-Seop Park ,  Gun-Hee Han ,  Seog-Heon Ham

    发明人： Ju-Seop Park ,  Gun-Hee Han ,  Seog-Heon Ham

    IPC分类号： H04N9/083 ,  H04N3/14 ,  H04N5/335 ,  H04N9/04

    CPC分类号： H04N5/235 ,  H04N5/2355

    摘要： A method for operating an image capture device having a sensor with an array of first and second pixels includes capturing an image a plurality of times with the second pixels to produce a corresponding second image signal, the second pixels being white pixels, capturing the image a single time with the first pixels to produce a corresponding first image signal, inputting selecting signals to the sensor via a row driver to obtain the first and second image signals from the first and second pixels, respectively, and converting the first and second image signals to respective digital values via an analog-to-digital converter.

    摘要翻译： 一种用于操作具有具有第一和第二像素的阵列的传感器的图像捕获装置的方法包括用第二像素捕获多次图像以产生对应的第二图像信号，第二像素为白色像素，捕获图像 与第一像素单时间产生对应的第一图像信号，经由行驱动器将选择信号输入到传感器，以分别从第一和第二像素获得第一和第二图像信号，并将第一和第二图像信号转换为 各自的数字值通过模数转换器。

    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    7.
    发明授权
    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
    防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法

    公开(公告)号：US08514648B2

    公开(公告)日：2013-08-20

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME 有权
    包括保险丝阵列的半导体器件及其操作方法

    公开(公告)号：US20120120733A1

    公开(公告)日：2012-05-17

    申请号：US13295484

    申请日：2011-11-14

    申请人： Jong-pil Son ,  Seong-jin Jang ,  Byung-sik Moon ,  Ju-seop Park

    发明人： Jong-pil Son ,  Seong-jin Jang ,  Byung-sik Moon ,  Ju-seop Park

    IPC分类号： G11C17/16 ,  G11C29/00 ,  G11C7/10

    CPC分类号： H01L27/101 ,  G11C17/14 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.

    摘要翻译： 提供一种包括熔丝的半导体器件及其操作方法。 半导体器件包括熔丝阵列，第一寄存器单元和第二寄存器单元。 熔丝阵列包括多个行和列。 第一寄存器单元从熔丝阵列接收至少一行熔丝数据。 至少一行熔丝数据的保险丝数据由第一寄存器单元并行接收。 第二寄存器单元从第一寄存器单元一次接收至少一个位的熔丝数据。

    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    9.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。