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    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    3.
    发明授权
    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
    防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法

    公开(公告)号：US08514648B2

    公开(公告)日：2013-08-20

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    4.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE 有权
    在半导体存储器件中产生内部电压的器件和方法

    公开(公告)号：US20090207674A1

    公开(公告)日：2009-08-20

    申请号：US12372290

    申请日：2009-02-17

    申请人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

    发明人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C5/147

    摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

    摘要翻译： 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为 当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

    Circuit and method for generating word line control signals and semiconductor memory device having the same
    7.
    发明授权
    Circuit and method for generating word line control signals and semiconductor memory device having the same 失效
    用于产生字线控制信号的电路和方法以及具有该字线控制信号的半导体存储器件

    公开(公告)号：US07206252B2

    公开(公告)日：2007-04-17

    申请号：US11141783

    申请日：2005-05-31

    申请人： Doo-Young Kim

    发明人： Doo-Young Kim

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10

    摘要： A circuit for generating word line control signals that have a stable boosting margin of the sub-word line driver: The circuit includes a first address buffer, a pre-decoder unit, a second address buffer, a main decoder and a circuit for generating a word-line boosting signal. The second address buffer delays a refresh count signal for a predetermined time and generates an enable signal having a predetermined pulse width in response to a row address setup signal and the delayed refresh count signal, and receives and latches a pre-decoded row address signals to output decoded row address signals in response to the enable signal. Accordingly, the circuit for generating word line control signals is capable of obtaining a stable self-boosting margin when the semiconductor memory device operates in a refresh mode.

    摘要翻译： 一种用于产生具有所述子字线驱动器的稳定升压裕度的字线控制信号的电路：所述电路包括第一地址缓冲器，预解码器单元，第二地址缓冲器，主解码器和用于产生 字线升压信号。 第二地址缓冲器将刷新计数信号延迟预定时间，并且响应于行地址建立信号和延迟刷新计数信号产生具有预定脉冲宽度的使能信号，并且接收并锁存预解码的行地址信号 响应于使能信号输出解码的行地址信号。 因此，当半导体存储器件以刷新模式工作时，用于产生字线控制信号的电路能够获得稳定的自增益裕度。

    Semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops
    8.
    发明授权
    Semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops 有权
    具有由多个反馈回路构成的阵列电压控制电路的半导体存储器件

    公开(公告)号：US06775199B2

    公开(公告)日：2004-08-10

    申请号：US10405770

    申请日：2003-04-01

    申请人： Doo-Young Kim ,  Byung-Chul Kim

    发明人： Doo-Young Kim ,  Byung-Chul Kim

    IPC分类号： G11C700

    CPC分类号： G11C5/147 ,  G11C5/14

    摘要： The invention discloses a semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops. In order to maintain constant the array voltage used for a single memory cell array region the plurality of feedback loops dividedly connect to a power line structure covering the memory cell array region, resulting in a reduction in the load to be taken by the output of feedback amplifiers to thereby achieve stable array voltage control operations.

    摘要翻译： 本发明公开了一种具有由多个反馈回路构成的阵列电压控制电路的半导体存储器件。 为了保持用于单个存储单元阵列区域的阵列电压恒定，多个反馈回路分别连接到覆盖存储单元阵列区域的电力线结构，导致由反馈的输出采取的负载减小 放大器，从而实现稳定的阵列电压控制操作。

    DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE 审中-公开
    在半导体存储器件中产生内部电压的器件和方法

    公开(公告)号：US20120213018A1

    公开(公告)日：2012-08-23

    申请号：US13462915

    申请日：2012-05-03

    申请人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

    发明人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

    IPC分类号： G11C7/00

    CPC分类号： G11C5/147

    摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

    摘要翻译： 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为 当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

    Layout structure of semiconductor memory device having IOSA
    10.
    发明授权
    Layout structure of semiconductor memory device having IOSA 有权
    具有IOSA的半导体存储器件的布局结构

    公开(公告)号：US07715261B2

    公开(公告)日：2010-05-11

    申请号：US12037326

    申请日：2008-02-26

    申请人： Doo-Young Kim ,  Byung-Chul Kim

    发明人： Doo-Young Kim ,  Byung-Chul Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C5/025 ,  G11C5/063

    摘要： Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output lines have less loading and therefore enable higher-speed data transfer rates. Some embodiments of the invention include column selection line repeaters between the two memory blocks. The column selection line repeaters reduce loading in the column selection lines, and increase column selection speed. Embodiments of the invention include both input/output sense amplifiers and column selection line repeaters disposed between the two memory blocks to increase data transfer rates on the global input/output lines and also increase column selection speed.

    摘要翻译： 本发明的实施例提供了一种用于将每个存储体分成两个块的半导体存储器件的布局。 本发明的实施例在两个存储块之间设置输入/输出读出放大器，以实现对存储体的所有区域的相对较短的全局输入/输出线。 更短的全局输入/输出线路的负载较少，因此可实现更高速度的数据传输速率。 本发明的一些实施例包括两个存储块之间的列选择线中继器。 列选择线中继器减少列选择行中的加载，并增加列选择速度。 本发明的实施例包括设置在两个存储器块之间的输入/输出读出放大器和列选择线中继器，以增加全局输入/输出线上的数据传输速率，并且还增加列选择速度。