公开(公告)号：US07990129B2

公开(公告)日：2011-08-02

申请号：US12476565

申请日：2009-06-02

申请人： Joon Young Kwak ,  Yoon-Hee Choi ,  Jin-Yub Lee ,  You-Sang Lee ,  Bo-Geun Kim

发明人： Joon Young Kwak ,  Yoon-Hee Choi ,  Jin-Yub Lee ,  You-Sang Lee ,  Bo-Geun Kim

IPC分类号： G05F3/16

CPC分类号： G05F3/08

摘要： A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

摘要翻译： 参考电压产生电路提供稳定的参考电压并且包括： 提供时钟信号的时钟发生器，响应于时钟信号提供泵浦电压的高电压发生器，通过从所述泵浦电压去除电压纹波提供静态电压的纹波消除器以及提供参考电压的参考电压发生器。

公开(公告)号：US20050135145A1

公开(公告)日：2005-06-23

申请号：US10957382

申请日：2004-09-30

申请人： You-Sang Lee ,  Jin-Yub Lee

发明人： You-Sang Lee ,  Jin-Yub Lee

IPC分类号： G11C16/02 ,  G11C8/18 ,  G11C11/00 ,  G11C16/32

CPC分类号： G11C16/32 ,  G11C8/18

摘要： A flash memory device includes a flash memory cell array, and an interface circuit, which receives a command and addresses sequentially in synchronization to an external system clock after a predetermined first latency is elapsed from when a chip enable signal is activated, in a read operation, in a program operation, and in an erase operation. The interface circuit receives the command in response to activation of an invoke signal. Therefore, since the flash memory device does not require CLE (Command Latch Enable) signals, ALE (Address Latch Enable) signals, RE (Read Enable) signals and WE (Write Enable) signals, internal circuits of the flash memory device can be simply controlled, thereby reducing a probability of skew generation in chips, improving performance, and decreasing the number of required pins.

摘要翻译： 闪速存储器件包括闪速存储单元阵列和接口电路，该接口电路在读取操作中从启动芯片使能信号起经过预定​​的第一等待时间之后，以与外部系统时钟同步的顺序接收命令和寻址 ，在编程操作中，以及擦除操作。 接口电路响应于调用信号的激活而接收命令。 因此，由于闪存器件不需要CLE（命令锁存使能）信号，ALE（地址锁存使能）信号，RE（读使能）信号和WE（写使能）信号，闪存器件的内部电路可以简单 从而降低了芯片中产生偏斜的可能性，提高了性能，并减少了所需引脚的数量。

公开(公告)号：US20080094071A1

公开(公告)日：2008-04-24

申请号：US11605224

申请日：2006-11-29

申请人： You-sang Lee ,  Jin-Yub Lee

发明人： You-sang Lee ,  Jin-Yub Lee

IPC分类号： G01R31/02

CPC分类号： G01R31/318566

摘要： A semiconductor device includes a plurality of fuses, and a plurality of latch circuits respectively electrically connected to the plurality of fuses. The plurality of latch circuits are configured to store respective fuse-cut information from the plurality of fuses, and to then sequentially transmit the fuse-cut information through the latch circuits to output sequential data indicative of a fuse-cut state of the plurality of fuses.

摘要翻译： 半导体器件包括多个保险丝，以及分别电连接到多个保险丝的多个锁存电路。 多个锁存电路被配置为存储来自多个保险丝的相应熔丝切断信息，然后通过锁存电路顺序地发送熔丝切断信息，以输出表示多个保险丝的熔丝切断状态的顺序数据 。

公开(公告)号：US08301829B2

公开(公告)日：2012-10-30

申请号：US13108687

申请日：2011-05-16

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F2212/7203

摘要： A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.

摘要翻译： 闪存器件包括闪存和缓冲存储器。 闪存分为主区域和备用区域。 缓冲存储器是随机存取存储器，并且具有与闪存相同的结构。 另外，闪存装置还包括控制装置，用于映射从主机应用的闪速存储器的地址，以将缓冲存储器的结构划分成主区域和备用区域，并用于控制闪速存储器和缓冲器 用于将缓冲存储器的数据存储在闪速存储器中或用于将闪存的数据存储在缓冲存储器中的存储器。

公开(公告)号：US07908425B2

公开(公告)日：2011-03-15

申请号：US12216003

申请日：2008-06-27

申请人： Jin-Yub Lee ,  Sang-Won Hwang

发明人： Jin-Yub Lee ,  Sang-Won Hwang

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0893 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2245

摘要： In a read method for a memory device, a bit line is set with data in a first memory cell; and the data on the bit line is stored in a register. The data in the register is transferred to a data bus while setting the bit line with data in a second memory cell. In another read method for a memory device, a bit line of a first memory cell is initialized and the bit line is pre-charged with a pre-charge voltage. Data in a memory cell on the bit line is developed, and a register corresponding to the bit line is initialized. The data on the bit line is stored in the register. The data in the register is output externally while performing the initializing, pre-charging, making and initializing to set the bit line with data in a second memory cell.

摘要翻译： 在存储器件的读取方法中，位线被设置在第一存储器单元中的数据中; 位线上的数据存储在寄存器中。 寄存器中的数据被传送到数据总线，同时在第二个存储单元中将位线设置为数据。 在存储器件的另一读取方法中，初始化第一存储器单元的位线，并且利用预充电电压对位线进行预充电。 开发位线上存储单元中的数据，初始化与位线对应的寄存器。 位线上的数据存储在寄存器中。 寄存器中的数据在执行初始化，预充电，制作和初始化时从外部输出，以将位线设置为第二个存储单元中的数据。

公开(公告)号：US07876613B2

公开(公告)日：2011-01-25

申请号：US12182274

申请日：2008-07-30

申请人： Sang-Chul Kang ,  Ho-kil Lee ,  Jin-Yub Lee

发明人： Sang-Chul Kang ,  Ho-kil Lee ,  Jin-Yub Lee

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

摘要翻译： 提供多位闪存设备。 该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。 每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。 缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。 提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较 程序。 控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

公开(公告)号：US07813184B2

公开(公告)日：2010-10-12

申请号：US11614413

申请日：2006-12-21

申请人： Hoo-Sung Kim ,  Hyung-Seok Kang ,  Jin-Yub Lee

发明人： Hoo-Sung Kim ,  Hyung-Seok Kang ,  Jin-Yub Lee

IPC分类号： G11C11/00

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/3445

摘要： Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.

摘要翻译： 提供了在包括多个存储器块的存储器件上执行多块擦除操作的方法。 根据这些方法，基于要擦除的存储块的数量来控制施加到在多块擦除操作期间被擦除的存储块的第一电压上升的速率。 存储器件可以是闪存器件，并且第一电压可以是施加到闪存器件的衬底的擦除电压。 可以设置第一电压上升的速率，使得闪存器件的衬底在大致相同的时间达到擦除电压电平，而与要擦除的存储器块的数量无关。

公开(公告)号：US07689741B2

公开(公告)日：2010-03-30

申请号：US10940038

申请日：2004-09-13

申请人： Eun-Suk Kang ,  Jin-Yub Lee

发明人： Eun-Suk Kang ,  Jin-Yub Lee

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G11C7/1075

摘要： A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.

摘要翻译： 提供了能够通过减少数据传输时间来提高系统性能的双缓冲存储器系统及其控制方法。 双缓冲存储器系统包括闪存块和多个缓冲器。 双缓冲存储器系统使用双缓冲方案，其中多个缓冲器中的一个缓冲器与闪存块交互，并且同时多个缓冲器中的不同缓冲器与主机交互。 因此，可以减少闪存与主机之间的数据传输时间，从而提高系统性能。

公开(公告)号：US07586790B2

公开(公告)日：2009-09-08

申请号：US11842995

申请日：2007-08-22

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/3495

摘要： A flash memory device is disclosed and includes a memory cell array comprising memory cells arranged in rows and columns, a page buffer circuit having a single latch structure and configured to read data from a selected page in the memory cell array, and a controller controlling the page buffer circuit to detect memory cells having an improper voltage distribution causes by charge leakage within the selected page.

摘要翻译： 公开了一种闪速存储器件，包括存储单元阵列，其包括以行和列排列的存储单元，具有单个锁存结构并被配置为从存储单元阵列中的选定页读取数据的页缓冲器电路，以及控制器 用于检测具有不正确的电压分布的存储单元的页缓冲电路是由选定页内的电荷泄漏引起的。

公开(公告)号：US07486557B2

公开(公告)日：2009-02-03

申请号：US11480236

申请日：2006-06-30

申请人： Jin-Kook Kim ,  Jin-Yub Lee

发明人： Jin-Kook Kim ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A method of programming a flash memory device includes charging selection lines with a first voltage while applying program data to bit lines to during a bit line setup interval, then activating a block word line to electrically connect the selection lines to corresponding word lines, and then applying a second voltage, greater than the first voltage, to a selected one of the selection lines. Related devices are also disclosed.

摘要翻译： 一种对闪速存储器件进行编程的方法包括：在位线建立间隔期间将程序数据应用于位线，然后激活块字线以将选择线电连接到对应的字线，然后将第一电压充电选择线，然后 将大于第一电压的第二电压施加到所选择的选择线之一。 还公开了相关设备。