公开(公告)号：US20050212562A1

公开(公告)日：2005-09-29

申请号：US11088506

申请日：2005-03-24

申请人： Jorg Gliese ,  Winfried Kamp ,  Siegmar Koppe ,  Michael Scheppler

发明人： Jorg Gliese ,  Winfried Kamp ,  Siegmar Koppe ,  Michael Scheppler

IPC分类号： H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L27/10 ,  H01L27/118 ,  H03K19/096 ,  H03K19/173

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US20050204274A1

公开(公告)日：2005-09-15

申请号：US11063953

申请日：2005-02-23

申请人： Winfried Kamp ,  Siegmar Koppe

发明人： Winfried Kamp ,  Siegmar Koppe

IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C29/00 ,  H03M13/00

CPC分类号： G11C15/04 ,  G06F11/1048 ,  G11C15/00 ,  G11C2029/0411

摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.

摘要翻译： 奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同 存储奇偶校验电路由相同电导型的四个晶体管形成。 奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。 检测器是自动状态设备的形式，并具有多个锁存器。

公开(公告)号：US07492187B2

公开(公告)日：2009-02-17

申请号：US11437421

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/1776

摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

摘要翻译： 用于在FPGA器件中提供配置数据的电路装置包括分配给FGPGA器件的各个可配置逻辑单元的多个输出触发器。 每个输出触发器包括至少一个数据输入和一个数据输出，并且多个输出触发器的第一输出触发器的数据输入可切换地连接到多个输出触发器的第二输出触发器的数据输出 用于通过集成在FPGA器件中的开关器件形成移位寄存器。

公开(公告)号：US20100308863A1

公开(公告)日：2010-12-09

申请号：US12780772

申请日：2010-05-14

申请人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

发明人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US07755110B2

公开(公告)日：2010-07-13

申请号：US11088506

申请日：2005-03-24

申请人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

发明人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

IPC分类号： H01L27/10

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US07439765B2

公开(公告)日：2008-10-21

申请号：US11437435

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/1778 ,  H01L2924/00

摘要： A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

摘要翻译： 掩模可编程逻辑宏包括至少三个输入端子，输出端子和由形成在半导体衬底上的至少三个晶体管组成的第一组晶体管，每个晶体管包括可控路径和控制端子。 可控路径可以通过金属化第一金属化区域而在第一电源端子和输出端子之间彼此串联连接。 第一组晶体管的晶体管以这样的方式被布置在半导体衬底上，使得可以通过金属化第一金属化区域之一来桥接晶体管的至少一个可控路径。 可以通过金属化第二金属化区域来将各个输入端子连接到相应的控制端子。

公开(公告)号：US20060279329A1

公开(公告)日：2006-12-14

申请号：US11437435

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/1778 ,  H01L2924/00

摘要： A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

摘要翻译： 掩模可编程逻辑宏包括至少三个输入端子，输出端子和由形成在半导体衬底上的至少三个晶体管组成的第一组晶体管，每个晶体管包括可控路径和控制端子。 可控路径可以通过金属化第一金属化区域而在第一电源端子和输出端子之间彼此串联连接。 第一组晶体管的晶体管以这样的方式被布置在半导体衬底上，使得可以通过金属化第一金属化区域之一来桥接晶体管的至少一个可控路径。 可以通过金属化第二金属化区域来将各个输入端子连接到相应的控制端子。

公开(公告)号：US20060273823A1

公开(公告)日：2006-12-07

申请号：US11437421

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/1776

摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

公开(公告)号：US07876893B2

公开(公告)日：2011-01-25

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

公开(公告)号：US20070047292A1

公开(公告)日：2007-03-01

申请号：US11444295

申请日：2006-05-31

申请人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

发明人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C14/009

摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.

摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。