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1.发明授权Reduced-power memory with per-sector power/ground control and early address 有权具有每扇区电源/地面控制和早期地址的降低功耗的存储器公开(公告)号：US07663961B1
公开(公告)日：2010-02-16
申请号：US11740901
申请日：2007-04-26
CPC分类号： G11C11/413 , G06F12/0895 , G06F2212/1028 , G11C7/20 , G11C8/14 , Y02D10/13
摘要： A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.
摘要翻译： 降低功率的存储器（例如用于处理器或微处理器的高速缓冲存储器系统）提供每扇区电源/地面控制和早期地址以有利地降低功耗。 降低功率存储器中包含的扇区的选择性功率控制响应于用于访问存储器的地址位的子集。 响应于访问，选择性功率控制单独地加电所选扇区中的一个扇区，然后在访问完成时关闭所选择的扇区。 上电是通过增加从保持差分到访问差分的电源和接地电平之间的差异。 通过在提供其他地址信息之前提供由选择性功率控制使用的地址信息来掩蔽差异所需的时间。 例如，在高速缓存中，标签访问与所选择的扇区的加电重叠，从而掩蔽对选定扇区加电的等待时间。
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公开(公告)号：US07443759B1
公开(公告)日：2008-10-28
申请号：US11740892
申请日：2007-04-26
CPC分类号： G11C11/413 , G06F12/0895 , G06F2212/1028 , G11C7/20 , G11C8/14 , Y02D10/13
摘要： A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.
摘要翻译： 降低功率的存储器（例如用于处理器或微处理器的高速缓冲存储器系统）提供每扇区地面控制以有利地降低功耗。 包含在所述降低功率存储器中的多个扇区的选择性功率控制响应于访问所述存储器的地址位的子集。 响应于访问，选择性功率控制单独地加电所选扇区中的一个扇区，然后在访问完成时关闭所选择的扇区。 上电是通过从保持级别到访问级别的地电位降低。 通过在提供其他地址信息之前提供由选择性功率控制使用的地址信息，可选地掩蔽了改变地电位所需的时间。 例如，在高速缓存中，标签访问与所选择的扇区的加电重叠，从而掩蔽对选定扇区加电的等待时间。
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公开(公告)号：US08225315B1
公开(公告)日：2012-07-17
申请号：US11933319
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
摘要翻译： 一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。 第一个虚拟内核映射到物理内核。 虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到 响应虚拟核心管理组件检测物理内核空闲的物理核心。
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公开(公告)号：US07797512B1
公开(公告)日：2010-09-14
申请号：US11933297
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/46
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.
摘要翻译： 包括一个或多个物理核心和一个或多个虚拟核心的虚拟核心管理系统。 每个虚拟核心分别包括与相应程序的执行相关联的逻辑状态的集合。 虚拟核心管理系统还包括一个或多个中断控制器，其被配置为发送一个或多个中断信号以中断与一个或多个虚拟核心中的至少一个虚拟核心相关联的对应程序的执行;以及虚拟核心管理组件， 至少一个虚拟内核到一个或多个物理核心中的一个，并将一个或多个中断信号路由到相应的物理核心。
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公开(公告)号：US07533242B1
公开(公告)日：2009-05-12
申请号：US11279880
申请日：2006-04-15
申请人： Laurent R. Moll , Jorel D. Hartman , Peter N. Glaskowsky , Seungyoon Peter Song , John Gregory Favor
发明人： Laurent R. Moll , Jorel D. Hartman , Peter N. Glaskowsky , Seungyoon Peter Song , John Gregory Favor
IPC分类号： G06F9/26
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F2212/1021 , G06F2212/6028
摘要： A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to execute instructions according to the instruction set architecture. The prefetch hints are directed to control operation of one or more hardware memory prefetcher units included in the processor, providing for increased efficiency in memory prefetching operations. The hints may optionally provide any combination of parameters describing a memory reference traffic pattern to search for, when to begin searching, when to terminate prefetching, and how aggressively to prefetch. Thus the hardware prefetchers are enabled to make improved traffic prediction, providing more accurate results using reduced hardware resources. The hints may include any combination of specific pattern hints (one/two/N-dimensional strides, indirect, and indirect-stride), modifiers including sparse and region, and a prefetch-stop directive. The parameters may include any combination of a count, a priority and a ramp.
摘要翻译： 软件代理装配在指令集架构中定义的预取提示指令或前缀，指令/前缀将预取提示信息传送到能够根据指令集架构执行指令的处理器。 预取提示旨在控制包括在处理器中的一个或多个硬件存储器预取器单元的操作，从而提高存储器预取操作的效率。 提示可以可选地提供描述存储器参考流量模式的参数的任何组合以搜索，何时开始搜索，何时终止预取，以及如何积极地预取。 因此，硬件预取器能够进行改进的流量预测，使用减少的硬件资源提供更准确的结果。 提示可以包括特定模式提示（一/二/ N维步幅，间接和间接步幅），包括稀疏和区域的修饰符以及预取停止指令的任何组合。 这些参数可以包括计数，优先级和斜坡的任何组合。
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6.发明授权Addressing scheme supporting fixed local addressing and variable global addressing 失效寻址方案支持固定的本地寻址和可变全局寻址公开(公告)号：US07340546B2
公开(公告)日：2008-03-04
申请号：US10439343
申请日：2003-05-15
IPC分类号： G06F13/22
CPC分类号： G06F13/4027 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/082 , G06F2212/2542
摘要： A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.
摘要翻译： 节点包括一个或多个资源以及可在使用期间用指示进行编程的寄存器。 一个或多个资源用地址空间的本地区域内的地址寻址。 所述指示标识所述地址空间的第二区域，所述第二区域被别名到所述局部区域，并且其他节点使用所述第二区域中的地址来寻址所述一个或多个资源。
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公开(公告)号：US07647452B1
公开(公告)日：2010-01-12
申请号：US11751949
申请日：2007-05-22
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0802 , G06F12/0804 , G06F12/0864 , G06F12/0888 , G06F12/0891 , G06F2212/1021 , G06F2212/1028 , G06F2212/2515 , G11C8/14 , G11C11/413 , G11C2207/2245 , Y02D10/13
摘要： A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or increasing performance. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. In some embodiments, less than the full tag portion is archived. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. In some embodiments, less than the full archive is restored. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.
摘要翻译： 重新获取高速缓冲存储器可以提高处理器的效率，例如降低功耗和/或提高性能。 当缓存存储器被禁用或暂时用于另一目的时，高速缓冲存储器的数据部分被刷新，并且标签部分被保存在存档中。 在一些实施例中，标签部分作为归档操作“就地”，并且在另外的实施例中，被放置在降低功率模式中。 在一些实施例中，小于完整标签部分被归档。 当高速缓冲存储器被重新启用或暂时使用完成时，可选地和/或选择性地，标签部分从归档重新填充，并且数据部分根据重新填充的标签部分重新获取。 在一些实施例中，恢复小于完整归档。 根据各种实施例，在以下的一个或多个中启用对高速缓存的处理器访问：保存; 重新填补 并重新获取。
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公开(公告)号：US06941406B2
公开(公告)日：2005-09-06
申请号：US10861624
申请日：2004-06-04
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F12/08 , G06F13/00 , G06F13/14 , G06F13/28 , G06F13/36 , G06F15/167 , H04L12/56 , H04Q11/00
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
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公开(公告)号：US07934054B1
公开(公告)日：2011-04-26
申请号：US11751973
申请日：2007-05-22
IPC分类号： G06F12/00
CPC分类号： G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0862 , G06F12/0891 , G06F12/0897 , G06F13/1694 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： A re-fetching cache memory improves efficiency of a system, for example by advantageously sharing the cache memory and/or by increasing performance. When some or all of the cache memory is temporarily used for another purpose, some or all of a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, some or all of the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the temporary use completes, optionally and/or selectively, at least some of the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.
摘要翻译： 重新获取高速缓冲存储器提高了系统的效率，例如有利地共享高速缓冲存储器和/或通过提高性能。 当部分或全部缓存存储器临时用于另一目的时，高速缓冲存储器的数据部分的一些或全部被刷新，并且一部分或全部标签部分被保存在存档中。 在一些实施例中，标签部分的一些或全部作为归档操作“就地”，并且在另外的实施例中，被放置在降低功率模式中。 当暂时使用完成时，可选地和/或选择性地，从归档重新填充标签部分的至少一些，并且根据重新填充的标签部分重新获取数据部分。 根据各种实施例，在以下的一个或多个中启用对高速缓存的处理器访问：保存; 重新填补 并重新获取。
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公开(公告)号：US07873788B1
公开(公告)日：2011-01-18
申请号：US11751985
申请日：2007-05-22
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0862 , G06F2212/1028 , G11C7/20 , Y02D10/13
摘要： A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or by advantageously sharing the cache memory. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from some or all of the archive, and the data portion is re-fetched according to the repopulated tag portion. The re-fetching is optionally performed in a cache coherent fashion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.
摘要翻译： 重新获取高速缓冲存储器可提高处理器的效率，例如通过降低功耗和/或有利地共享高速缓冲存储器。 当高速缓冲存储器被禁用或临时用于另一目的时，高速缓冲存储器的数据部分被刷新，并且标签部分中的一些或全部被保存在归档中。 在一些实施例中，标签部分作为归档操作“就地”，并且在另外的实施例中，被放置在降低功率模式中。 当高速缓冲存储器被重新启用或临时使用完成时，可选地和/或选择性地，标签部分从档案的一些或全部重新填充，并且根据重新填充的标签部分重新获取数据部分。 重新获取可选地以缓存一致的方式执行。 根据各种实施例，在以下的一个或多个中启用对高速缓存的处理器访问：保存; 重新填补 并重新获取。
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