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公开(公告)号：US4987578A
公开(公告)日：1991-01-22
申请号：US254751
申请日：1988-10-07
IPC分类号： G06F13/36 , G06F13/40 , H03K19/018 , H03K19/173
CPC分类号： H03K19/1735 , G06F13/4027 , H03K19/01806 , H03K19/01812
摘要： A customizable communications bus control gate array for facilitating communications between devices on two disparate digital communications channels. The gate array has a mask programmable integrated circuit with two I/O interface devices which are respectively connected to two different communications channels. The gate array also has a translating device connected to each of the I/O interface devices for translating electrical signals therebetween. Logic control is also provided and connected to both of the I/O interface device and to the translating device for controlling operations thereof so that predetermined communications requirements between both of the disparate communications channels are satisfied.
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公开(公告)号：US5184034A
公开(公告)日：1993-02-02
申请号：US804906
申请日：1991-12-06
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/08 , H03K19/082 , H03K19/088 , H03K19/0944
CPC分类号： H03K19/0826 , H03K19/00307 , H03K19/09448
摘要： A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode. This other path provides discharge protection for the base of the pullup transistor for the buffer in its inactive mode, and has incorporated into it reverse breakdown protection in the form of voltage drop devices such as forward-biased diodes.
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公开(公告)号：US5223745A
公开(公告)日：1993-06-29
申请号：US930471
申请日：1992-08-14
IPC分类号： H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/01 , H03K19/013 , H03K19/017 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/0136 , H03K19/0016 , H03K19/01721
摘要： A circuit to be used with bistate and tristate output buffers as a means of diverting from the output pulldown transistor Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a MOS transistor coupled between the output pulldown transistor and the lower potential power rail of the output buffer. This MOS transistor is controlled by another MOS transistor coupled to output V.sub.OUT of the buffers. This driver transistor is controlled by the high potential power rail of the buffer and so turns on the Miller Current Discharge Transistor only when the buffer is powered down. The invention also encompasses a discharge transistor coupled to the data input V.sub.IN to ensure that the Miller Current Discharge Transistor never pulls the of the output pulldown when the buffer is in its active low state.
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公开(公告)号：US5021687A
公开(公告)日：1991-06-04
申请号：US473533
申请日：1990-02-01
申请人： Roy Yarbrough , Ernest D. Haacke , Lars G. Jansson
发明人： Roy Yarbrough , Ernest D. Haacke , Lars G. Jansson
IPC分类号： H03K17/66 , H03K3/037 , H03K3/2893 , H03K19/003 , H03K19/088
CPC分类号： H03K3/0377 , H03K19/00353 , H03K3/2893
摘要： A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.
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