Cylinder sleeve for an internal combustion engine and block of cylinders which are equipped with one such sleeve
    1.
    发明授权
    Cylinder sleeve for an internal combustion engine and block of cylinders which are equipped with one such sleeve 有权
    用于内燃机的缸套和装有一个这样的套筒的气缸体

    公开(公告)号:US08695558B2

    公开(公告)日:2014-04-15

    申请号:US11993845

    申请日:2006-06-28

    IPC分类号: F02F1/00

    CPC分类号: F02F1/004 F02F2001/008

    摘要: The invention relates to a cylinder sleeve (2) for lining the cylindrical wall of a cylinder (A1) of an internal combustion engine. The inventive sleeve (2) comprises an inner wall (3) which is intended to guide a piston in translation and an outer wall (4) which is intended to rest on the cylindrical wall of the cylinder. The outer wall (4) of the sleeve of the cylinder (2) comprises an upper part (6) which is flared toward a top edge (5) of the sleeve (2), which is defined between the inner (3) and outer (4) walls of the cylinder sleeve. The invention also relates to a cylinder block of an internal combustion engine, comprising at least two cylinders (A1, B1) which are each equipped with one such cylinder sleeve.

    摘要翻译: 本发明涉及一种用于衬套内燃机的气缸(A1)的圆筒壁的气缸套筒(2)。 本发明的套筒(2)包括旨在引导平移的活塞的内壁(3)和旨在搁置在气缸的圆柱形壁上的外壁(4)。 气缸(2)的套管的外壁(4)包括朝向套筒(2)的顶部边缘(5)扩张的上部(6),其限定在内部(3)和外部 (4)气缸套的壁。 本发明还涉及一种内燃机的气缸体,其包括至少两个气缸(A1,B1),每个气缸均配备有一个这样的气缸套筒。

    CYLINDER SLEEVE FOR AN INTERNAL COMBUSTION ENGINE AND BLOCK OF CYLINDERS WHICH ARE EQUIPPED WITH ONE SUCH SLEEVE
    2.
    发明申请
    CYLINDER SLEEVE FOR AN INTERNAL COMBUSTION ENGINE AND BLOCK OF CYLINDERS WHICH ARE EQUIPPED WITH ONE SUCH SLEEVE 有权
    用于内燃机的气缸套筒和装有一个这样的套筒的缸体块

    公开(公告)号:US20100263619A1

    公开(公告)日:2010-10-21

    申请号:US11993845

    申请日:2006-06-28

    IPC分类号: F02F1/00

    CPC分类号: F02F1/004 F02F2001/008

    摘要: The invention relates to a cylinder sleeve (2) for lining the cylindrical wall of a cylinder (A1) of an internal combustion engine. The inventive sleeve (2) comprises an inner wall (3) which is intended to guide a piston in translation and an outer wall (4) which is intended to rest on the cylindrical wall of the cylinder. The outer wall (4) of the sleeve of the cylinder (2) comprises an upper part (6) which is flared toward a top edge (5) of the sleeve (2), which is defined between the inner (3) and outer (4) walls of the cylinder sleeve. The invention also relates to a cylinder block of an internal combustion engine, comprising at least two cylinders (A1, B1) which are each equipped with one such cylinder sleeve.

    摘要翻译: 本发明涉及一种用于衬套内燃机的气缸(A1)的圆筒壁的气缸套筒(2)。 本发明的套筒(2)包括旨在引导平移的活塞的内壁(3)和旨在搁置在气缸的圆柱形壁上的外壁(4)。 气缸(2)的套管的外壁(4)包括朝向套筒(2)的顶部边缘(5)扩张的上部(6),其限定在内部(3)和外部 (4)气缸套的壁。 本发明还涉及一种内燃机的气缸体,其包括至少两个气缸(A1,B1),每个气缸均配备有一个这样的气缸套筒。

    Electronic component having a molded component housing
    3.
    发明授权
    Electronic component having a molded component housing 有权
    具有模制部件壳体的电子部件

    公开(公告)号:US09408319B2

    公开(公告)日:2016-08-02

    申请号:US14094272

    申请日:2013-12-02

    摘要: An electronic component having a molded component housing and an electrically conductive insert part embedded in the component housing for contacting a micro component, the insert part having an accommodating area for accommodating the micro component with a subarea, which is spaced apart from the micro component, for decoupling the micro component from material stresses of the component housing. A method for manufacturing an electronic component having a molded component housing, an electrically conductive insert part for contacting a micro component being embedded in the component housing, a subarea, which is spaced apart from the micro component, decoupling the micro component from material stresses of the component housing, during curing of the housing material, in an accommodating area for accommodating the micro component on the insert part.

    摘要翻译: 一种电子部件,其具有模制部件壳体和嵌入在所述部件壳体中用于接触微型部件的导电插入部件,所述插入部分具有用于容纳所述微型部件的容纳区域,所述区域与所述微型部件间隔开, 用于将微组件与组件壳体的材料应力分离。 一种用于制造具有模制部件壳体的电子部件的方法,用于接触嵌入在所述部件壳体中的微型部件的导电插入部分,与所述微型部件间隔开的子区域,其将所述微型部件与材料应力 所述部件壳体在所述外壳材料的固化期间在用于将所述微型部件容纳在所述插入部件上的容纳区域中。

    Method for ASK demodulation, and ASK demodulator
    4.
    发明授权
    Method for ASK demodulation, and ASK demodulator 有权
    ASK解调方法和ASK解调器

    公开(公告)号:US06307428B1

    公开(公告)日:2001-10-23

    申请号:US09850586

    申请日:2001-05-07

    IPC分类号: H03D100

    摘要: A method for demodulating a voltage which has been ASK modulated by changing the amplitude between a low level and a high level, in particular for use during contactless data transmission from a card reader/writer to a smart card, is described. The method is distinguished, in that, in an initialization phase, a first mean value is produced from the high voltage level and a stored partial voltage derived therefrom in order to detect a change to a low voltage level. The change to the low voltage level represents a start value and is detected by a subsequent comparison of the modulated voltage with the first mean value. In a subsequent demodulation phase, a second mean value is produced from the detected low voltage level and the high voltage level in order to demodulate the modulated voltage by comparing the modulated voltage with the second mean value.

    摘要翻译: 描述了通过改变低电平和高电平之间的幅度来调制ASK的电压的方法,特别是用于在从读卡器/写卡器到智能卡的非接触式数据传输期间使用的电压。 该方法的区别在于,在初始化阶段中,从高电压电平产生第一平均值和从其导出的存储的部分电压,以便检测到低电压电平的变化。 对低电压电平的变化表示起始值,并且通过随后的调制电压与第一平均值的比较来检测。 在随后的解调阶段,从检测到的低电压电平和高电压电平产生第二平均值,以通过将调制电压与第二平均值进行比较来解调调制电压。

    Signal converter circuit
    6.
    发明申请
    Signal converter circuit 审中-公开
    信号转换电路

    公开(公告)号:US20070252618A1

    公开(公告)日:2007-11-01

    申请号:US11413315

    申请日:2006-04-28

    IPC分类号: H03K19/094

    CPC分类号: H03K19/0185 H03K19/09432

    摘要: A signal converter circuit including an input circuit and an output circuit. The input circuit is configured to receive current mode logic signals and provide differential input signals based on the current mode logic signals. The output circuit is configured to receive the differential input signals and provide rail-to-rail output signals based on the differential input signals. The output circuit is configured to switch the rail-to-rail output signals in response to a common edge type in each of the differential input signals.

    摘要翻译: 一种包括输入电路和输出电路的信号转换器电路。 输入电路被配置为接收电流模式逻辑信号并且基于当前模式逻辑信号提供差分输入信号。 输出电路被配置为接收差分输入信号并且基于差分输入信号提供轨到轨输出信号。 输出电路被配置为响应于每个差分输入信号中的公共边缘类型来切换轨到轨输出信号。

    Device for encapsulating a component with plastics material
    8.
    发明授权
    Device for encapsulating a component with plastics material 有权
    用塑料材料封装组件的装置

    公开(公告)号:US09120258B2

    公开(公告)日:2015-09-01

    申请号:US14123432

    申请日:2012-05-24

    IPC分类号: B29C45/14

    摘要: The invention relates to a device (10; 10a) for encapsulating a component (1) with plastic material (2), comprising at least two tool parts (11, 12), which in a closed arrangement for encapsulating the component (1) form a receptacle (15) for the component (1), an injection channel (30) for supplying the liquefied plastic material (2) to the region of the receptacle (15), and a single retaining element (22) for positioning the component (1) in the receptacle (15), wherein the retaining element (22) can be moved in a first position for positioning the component (1) in the receptacle (15) and in a second position for preferably completely encapsulating the component (1) with the plastic material (2). According to the invention, the retaining element (22) holds the component (1) in the region of the receptacle (15) by means of form positive and/or clamping engagement.

    摘要翻译: 本发明涉及一种用于用塑料材料(2)封装部件(1)的装置(10; 10a),其包括至少两个工具部件(11,12),所述工具部件在封闭装置中用于将部件(1)形成 用于组件(1)的容器(15),用于将液化塑料材料(2)供应到容器(15)的区域的注入通道(30)和用于定位组件的单个保持元件(22) 1)在容器(15)中,其中保持元件(22)可以在第一位置移动,用于将部件(1)定位在容器(15)中,并且在第二位置优选地完全包封部件(1) 与塑料(2)。 根据本发明,保持元件(22)通过形式的正和/或夹紧接合将部件(1)保持在容器(15)的区域中。

    Clock data recovery circuit with circuit loop disablement
    9.
    发明授权
    Clock data recovery circuit with circuit loop disablement 有权
    具有电路回路禁止的时钟数据恢复电路

    公开(公告)号:US07681063B2

    公开(公告)日:2010-03-16

    申请号:US11093554

    申请日:2005-03-30

    IPC分类号: G06F11/00 H04L27/00 H04L7/00

    摘要: A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

    摘要翻译: 时钟数据恢复电路包括第一电路,第二电路和第三电路。 第一电路被配置为接收数据和时钟信号并且检测数据中的转变并且基于时钟信号和数据中的转换来提供第一信号。 第二电路被配置为接收第一信号并且基于第一信号提供第一移位信号。 第三电路被配置为接收第一移位信号,其中第一电路,第二电路和第三电路被配置为形成第一电路回路,并且第三电路被配置为禁用第一电路回路并且移位时钟信号 基于第一移位信号。

    Clock data recovery circuit with circuit loop disablement
    10.
    发明申请
    Clock data recovery circuit with circuit loop disablement 有权
    具有电路回路禁止的时钟数据恢复电路

    公开(公告)号:US20060227914A1

    公开(公告)日:2006-10-12

    申请号:US11093554

    申请日:2005-03-30

    IPC分类号: H04L7/00

    摘要: A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

    摘要翻译: 时钟数据恢复电路包括第一电路,第二电路和第三电路。 第一电路被配置为接收数据和时钟信号并且检测数据中的转变并且基于时钟信号和数据中的转换来提供第一信号。 第二电路被配置为接收第一信号并且基于第一信号提供第一移位信号。 第三电路被配置为接收第一移位信号,其中第一电路,第二电路和第三电路被配置为形成第一电路回路,并且第三电路被配置为禁用第一电路回路并且移位时钟信号 基于第一移位信号。