公开(公告)号：US06734491B1

公开(公告)日：2004-05-11

申请号：US10331705

申请日：2002-12-30

申请人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

发明人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

公开(公告)号：US20050221595A1

公开(公告)日：2005-10-06

申请号：US11145460

申请日：2005-06-02

申请人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

发明人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。

公开(公告)号：US06908859B2

公开(公告)日：2005-06-21

申请号：US10267264

申请日：2002-10-08

申请人： Sameer P. Pendharkar ,  Taylor R. Efland ,  William Nehrer

发明人： Sameer P. Pendharkar ,  Taylor R. Efland ,  William Nehrer

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78 ,  H01L21/302

CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L21/823493 ,  H01L29/1045 ,  H01L29/7835

摘要： A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

摘要翻译： 晶体管形成在半导体衬底中。 深n井区域与浅的n阱区域结合使用。 轻掺杂漏极延伸区域设置在漏极区域和栅极导体之间​​。 区域的使用和区域的背景提供了非常高的击穿电压，与器件的相对低的沟道电阻相比。