公开(公告)号：US06734491B1

公开(公告)日：2004-05-11

申请号：US10331705

申请日：2002-12-30

申请人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

发明人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

公开(公告)号：US06930005B2

公开(公告)日：2005-08-16

申请号：US10725642

申请日：2003-12-02

申请人： Taylor R. Efland ,  Jozef C. Mitros ,  Imran Khan

发明人： Taylor R. Efland ,  Jozef C. Mitros ,  Imran Khan

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).

摘要翻译： 一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。 该方法提供第一导电类型的第一阱（50​​2），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。 相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。 第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。 该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。 接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。

公开(公告)号：US06873021B1

公开(公告)日：2005-03-29

申请号：US10725641

申请日：2003-12-02

申请人： Jozef C. Mitros ,  Imran Khan ,  Taylor R. Efland

发明人： Jozef C. Mitros ,  Imran Khan ,  Taylor R. Efland

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

摘要： A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable as the extension of the transistor drain (305) of the first conductivity type, and covered by a first insulator (312) having a first thickness, and further a second well (302) of the opposite conductivity type, intended to contain the transistor source (304) of the first conductivity type, and covered by a second insulator (311) thinner than said first insulator (312). First and second wells form a junction (330) that terminates (320, 321) at the second insulator. The first well has a region (360) in the proximity of the junction termination, which has a higher doping concentration than the remainder of the first well and extends not deeper than the first insulator thickness. Region (360) of higher doping concentration reduces the transistor drain resistance so that the drain current is increased to approximately twice the value it had without the higher doping concentration, while the transistor breakdown voltage remains determined by the (low) doping concentration of the remainder of first well (315).

摘要翻译： 第一导电类型的半导体晶片（300）中的漏极扩展MOS晶体管包括第一导电类型的第一阱（315），可用作第一导电类型的晶体管漏极（305）的延伸部分，并且被覆盖 通过具有第一厚度的第一绝缘体（312）和另外具有相反导电类型的第二阱（302），用于容纳第一导电类型的晶体管源（304），并被第二绝缘体（311）覆盖， 比所述第一绝缘体（312）薄。 第一和第二阱形成在第二绝缘体处终止（320,321）的结（330）。 第一阱具有在接合端子附近的区域（360），其具有比第一阱的其余部分更高的掺杂浓度，并且延伸不比第一绝缘体厚度更深。 掺杂浓度较高的区域（360）降低了晶体管漏极电阻，使得漏极电流增加到其没有较高掺杂浓度的值的两倍，而晶体管击穿电压保持由其余部分的（低）掺杂浓度确定 的第一井（315）。

公开(公告)号：US20050221595A1

公开(公告)日：2005-10-06

申请号：US11145460

申请日：2005-06-02

申请人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

发明人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。

公开(公告)号：US20200334253A1

公开(公告)日：2020-10-22

申请号：US16765508

申请日：2018-11-20

申请人： Charbel Joseph El Kaed ,  Imran Khan ,  Hicham Hossayni

发明人： Charbel Joseph El Kaed ,  Imran Khan ,  Hicham Hossayni

IPC分类号： G06F16/2452 ,  G06F16/36 ,  G06F16/2458 ,  G06F17/18

摘要： Methods and systems are provided for searching time series information in a distributed data processing system. A method of processing a semantic search query comprises receiving a structured search query, processing the structured search query to deconstruct into query elements, identifying a set of connected elements based on the query elements, processing a time series data structure of the identified set of connected elements to determine a command data element, utilizing the command data element to process the time series data structure of the identified set of connected elements, annotating the time series data structure of each of the identified set of connected elements to form a queried data set, and providing the queried data set.

公开(公告)号：US08536011B2

公开(公告)日：2013-09-17

申请号：US13074836

申请日：2011-03-29

申请人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

发明人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L29/788

CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

摘要翻译： 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

公开(公告)号：US06958269B2

公开(公告)日：2005-10-25

申请号：US10178100

申请日：2002-06-24

申请人： Josef Czeslaw Mitros ,  Imran Khan ,  Lily Springer

发明人： Josef Czeslaw Mitros ,  Imran Khan ,  Lily Springer

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/236 ,  H01L29/745

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.

摘要翻译： 一种用于制造存储器件的方法包括在衬底附近形成氧化物层。 形成浮栅，并从氧化物层向外设置。 形成介电层，使得其从浮栅层向外设置。 然后，形成导电材料层并从电介质层向外设置导电材料层，其中导电材料层形成通过介电层基本上与浮动栅极隔离的控制栅极。

公开(公告)号：US09054632B2

公开(公告)日：2015-06-09

申请号：US13198256

申请日：2011-08-04

申请人： James Hinkle ,  Imran Khan ,  Modesto Sanchez ,  Thomas Truman

发明人： James Hinkle ,  Imran Khan ,  Modesto Sanchez ,  Thomas Truman

IPC分类号： G01R31/26 ,  H02S50/10 ,  G01R1/073

CPC分类号： H02S50/10 ,  G01R1/07342

摘要： Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods. By providing deformable electrical contacts against a partially assembled module on an assembly line, an electrical bias can be applied to the module before the module is completely assembled. An electrical connection apparatus for a photovoltaic module may include a first contact configured to engage a first lead on the photovoltaic module, a second contact configured to engage a second lead on the photovoltaic module, and an electrical power source configured to apply an electrical bias between the first contact and the second contact.

摘要翻译： 可以使用电连接装置和方法来确定部分组装的光伏模块的特性。 通过向装配线上的部分组装的模块提供可变形的电触点，在模块完全组装之前，可以将电偏压施加到模块。 用于光伏模块的电连接装置可以包括被配置为接合光伏模块上的第一引线的第一触点，被配置为接合光伏模块上的第二引线的第二触点和被配置为在光伏模块之间施加电偏压的电源 第一次接触和第二次接触。

公开(公告)号：US20120230235A1

公开(公告)日：2012-09-13

申请号：US13411146

申请日：2012-03-02

申请人： Michelle Perras ,  Juan Carlos Zuniga ,  Alexander Reznik ,  Reeteshkumar Varshney ,  Imran Khan

发明人： Michelle Perras ,  Juan Carlos Zuniga ,  Alexander Reznik ,  Reeteshkumar Varshney ,  Imran Khan

IPC分类号： H04W4/00

CPC分类号： H04L69/22 ,  H04L69/14 ,  H04W28/06

摘要： Embodiments contemplate one or more techniques for packet filtering. One or more embodiments may apply specific routing and/or forwarding rules on some or each packet when a device has one or more, or multiple, interfaces. Contemplated filtering techniques may be implemented in a module and/or without modifying an IP stack. The contemplated packet filtering techniques may apply to a terminal in uplink and/or downlink as well as to any network node. An incoming packet table may be created using 5-tuple, 6-tuple, and/or tags, among other mechanisms, to support incoming and/or outgoing packet filtering.

摘要翻译： 实施例考虑了一种或多种用于分组过滤的技术。 一个或多个实施例可以在设备具有一个或多个或多个接口时在一些或每个分组上应用特定路由和/或转发规则。 考虑过滤技术可以在模块中实现和/或不修改IP堆栈。 预期的分组过滤技术可以应用于上行链路和/或下行链路中的终端以及任何网络节点。 可以使用5元组，6元组和/或标签以及其他机制来创建输入分组表，以支持传入和/或传出分组过滤。

公开(公告)号：US20120098045A1

公开(公告)日：2012-04-26

申请号：US13267674

申请日：2011-10-06

申请人： Weidong Tian ,  Imran Khan

发明人： Weidong Tian ,  Imran Khan

IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L29/92

CPC分类号： H01L28/40 ,  H01L27/0629 ,  H01L29/94

摘要： A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.

摘要翻译： 零温度系数（ZTC）电容器，其包括磷密度在1.7×1020原子/ cm3至2.3×1020原子/ cm3之间的二氧化硅介电层。 一种包含ZTC电容器的集成电路，其包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅电介质层。 形成包含Zinc电容器的集成电路的过程，该电容器包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅介电层。