公开(公告)号：US06908859B2

公开(公告)日：2005-06-21

申请号：US10267264

申请日：2002-10-08

申请人： Sameer P. Pendharkar ,  Taylor R. Efland ,  William Nehrer

发明人： Sameer P. Pendharkar ,  Taylor R. Efland ,  William Nehrer

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78 ,  H01L21/302

CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L21/823493 ,  H01L29/1045 ,  H01L29/7835

摘要： A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

摘要翻译： 晶体管形成在半导体衬底中。 深n井区域与浅的n阱区域结合使用。 轻掺杂漏极延伸区域设置在漏极区域和栅极导体之间​​。 区域的使用和区域的背景提供了非常高的击穿电压，与器件的相对低的沟道电阻相比。

公开(公告)号：US6160290A

公开(公告)日：2000-12-12

申请号：US196879

申请日：1998-11-20

申请人： Sameer P. Pendharkar ,  Taylor R. Efland

发明人： Sameer P. Pendharkar ,  Taylor R. Efland

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7835 ,  H01L29/402 ,  H01L29/7813

摘要： A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at least one-half of the length of the field oxide layer (20).

公开(公告)号：US06468837B1

公开(公告)日：2002-10-22

申请号：US09630594

申请日：2000-08-01

申请人： Sameer P. Pendharkar ,  Taylor R. Efland

发明人： Sameer P. Pendharkar ,  Taylor R. Efland

IPC分类号： H01L21332

CPC分类号： H01L29/7835 ,  H01L29/402 ,  H01L29/7813

摘要： A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at least one-half of the length of the field oxide layer (20).

摘要翻译： 半导体器件（10）包括减小的表面场（RESURF）植入物（14）。 具有长度的场氧化物层（20）形成在RESURF植入物（14）上。 场板（12）从场氧化物层（20）的近侧延伸并且在场氧化物层（20）的长度的至少一半上延伸。

公开(公告)号：US06225673B1

公开(公告)日：2001-05-01

申请号：US09257307

申请日：1999-02-25

申请人： Sameer P. Pendharkar ,  Taylor R. Efland

发明人： Sameer P. Pendharkar ,  Taylor R. Efland

IPC分类号： H01L2900

CPC分类号： H01L29/0847 ,  H01L21/761 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/7835

摘要： An integrated circuit (13) includes a P-epi substrate (51) having first and second n+ isolation layers (53, 54) buried therein, the first and second isolation layers being respectively coupled to ground and to a supply voltage (VCC). A contact region (52) of the substrate is closely adjacent a first isolation layer, is spaced from the second isolation layer, and is coupled to ground. First and second P-epi portions (57, 58) of the substrate are disposed within the first and second isolation layers. The first portion includes an n+ source region (62) disposed in a p-well (61) which is closely adjacent the first isolation layer in the vicinity of the contact region, and includes an n+ drain region (68). The second portion includes an n+ source region (77) coupled to the drain region in the first portion, and an n+ drain region (82) coupled to the supply voltage.

摘要翻译： 集成电路（13）包括具有埋入其中的第一和第二n +隔离层（53,54）的P外延衬底（51），第一和第二隔离层分别耦合到地和电源电压（VCC）。 衬底的接触区域（52）与第一隔离层紧密相邻，与第二隔离层隔开，并与地面相连。 衬底的第一和第二P-epi部分（57,58）设置在第一和第二隔离层内。 第一部分包括设置在p阱（61）中的在接触区域附近紧邻第一隔离层的n +源极区域（62），并且包括n +漏极区域（68）。 第二部分包括耦合到第一部分中的漏极区域的n +源极区域（77）和耦合到电源电压的n +漏极区域（82）。

公开(公告)号：US20090325352A1

公开(公告)日：2009-12-31

申请号：US12552471

申请日：2009-09-02

申请人： Sameer P. Pendharkar

发明人： Sameer P. Pendharkar

IPC分类号： H01L29/78 ,  H01L29/36

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/41 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/66659 ,  H03K19/00384

摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.

摘要翻译： 晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。 晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。 在第一半导体区域和第二半导体区域之间存在界面。 晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。 还描述了一种混合技术电路。

公开(公告)号：US07414287B2

公开(公告)日：2008-08-19

申请号：US11063312

申请日：2005-02-21

申请人： Sameer P. Pendharkar ,  Jonathan S. Brodsky

发明人： Sameer P. Pendharkar ,  Jonathan S. Brodsky

IPC分类号： H01L29/94

CPC分类号： H01L29/66681 ,  H01L27/088 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/7816

摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

摘要翻译： 半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。 每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区， 第二导电类型。 每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。 阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

公开(公告)号：US06670685B2

公开(公告)日：2003-12-30

申请号：US10155543

申请日：2002-05-24

申请人： Sameer P. Pendharkar

发明人： Sameer P. Pendharkar

IPC分类号： H01L31119

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.

摘要翻译： 高电压半导体器件包括设置在半导体衬底内的漏区。 半导体器件还包括从半导体衬底的漏极区域向外设置的场氧化物层。 半导体器件还包括从场氧化物层的至少一部分向内设置的浮动环结构。 在一个具体实施例中，与半导体器件相关联的器件参数劣化包括在加速寿命操作大约五百（500）秒之后的一个百分之一或更少。

公开(公告)号：US06624481B1

公开(公告)日：2003-09-23

申请号：US10407037

申请日：2003-04-04

申请人： Sameer P. Pendharkar ,  Philip L. Hower ,  Robert Steinhoff

发明人： Sameer P. Pendharkar ,  Philip L. Hower ,  Robert Steinhoff

IPC分类号： H01L2362

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).

摘要翻译： 包括第一和第二双极元件（210,220）的ESD坚固的双极晶体管（200），其中第一双极元件（210）的第一触发电压接近第二双极元件（220）的第二维持电压。 第一和第二双极元件（210,220）分别包括第一和第二基极（214,224），发射极（216,226）和集电极（212,222）。 耦合第一和第二基极（214,224），并且耦合第一和第二集电极（212,222）。 ESD稳健双极晶体管（200）还包括发射极电阻（250）和基极电阻（260），其中发射极电阻（250）将第一和第二发射极（216,226）和基极电阻（260）耦合 第二发射器（226）和第一和第二基极（214,224）。

公开(公告)号：US08754469B2

公开(公告)日：2014-06-17

申请号：US13281260

申请日：2011-10-25

申请人： Sameer P. Pendharkar ,  John Lin

发明人： Sameer P. Pendharkar ,  John Lin

IPC分类号： H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7816

摘要： An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

摘要翻译： 集成电路包括具有并行交替有源间隙漂移区和场间隙漂移区的扩展漏极MOS晶体管。 扩展漏极MOS晶体管包括在场间隙漂移区域上具有场板的栅极。 扩展漏极MOS晶体管可以形成为对称嵌套配置。 用于形成包含延伸漏极MOS晶体管的集成电路的工艺提供并行的交替有源间隙漂移区域和场间隙漂移区域，栅极在场间隙漂移区域上具有场板。

公开(公告)号：US08598008B2

公开(公告)日：2013-12-03

申请号：US13277939

申请日：2011-10-20

申请人： Sameer P. Pendharkar ,  Marie Denison ,  Yongxi Zhang

发明人： Sameer P. Pendharkar ,  Marie Denison ,  Yongxi Zhang

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/082 ,  H01L21/8222 ,  H01L27/0259 ,  H01L27/0823 ,  H01L29/735

摘要： An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

摘要翻译： 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。