Fabrication Method of Thin Film and Metal Line in Semiconductor Device
    3.
    发明申请
    Fabrication Method of Thin Film and Metal Line in Semiconductor Device 审中-公开
    半导体器件薄膜和金属线的制造方法

    公开(公告)号:US20070166985A1

    公开(公告)日:2007-07-19

    申请号:US11614101

    申请日:2006-12-21

    申请人: Han Choon Lee

    发明人: Han Choon Lee

    IPC分类号: H01L21/44

    CPC分类号: H01L21/76861 H01L21/76856

    摘要: A method for fabricating a thin layer in a semiconductor device is provided. The method can include: forming a preliminary layer, in which Ta and F are mixed, on a semiconductor substate by performing an Atomic Layer Deposition (ALD) method; forming a Ta layer by reacting the preliminary layer with B2H6; and forming a TaN layer by performing heat treatment for the Ta layer in N2 atmosphere.

    摘要翻译: 提供了一种在半导体器件中制造薄层的方法。 该方法可以包括:通过执行原子层沉积(ALD)方法在半导体子状态上形成混合有Ta和F的预备层; 通过使预备层与B 2 H 6 C反应形成Ta层; 并通过在N 2气氛中对Ta层进行热处理而形成TaN层。

    Image Sensor and Method for Manufacturing the Same
    4.
    发明申请
    Image Sensor and Method for Manufacturing the Same 审中-公开
    图像传感器及其制造方法

    公开(公告)号:US20090095968A1

    公开(公告)日:2009-04-16

    申请号:US12209331

    申请日:2008-09-12

    IPC分类号: H01L33/00 H01L21/00

    摘要: Provided are an image sensor and a method for manufacturing the same. A trench can be formed through metal interconnection layers of the image sensor in a region corresponding to a light receiving device for each unit pixel. A passivation layer pattern can be provided at sidewalls of the trench to inhibit light incident into the metal interconnection layers and reduce cross-talk and noise. A filler material can be provided to fill the trench. A color filter layer and microlens can be formed on the filler material. The filler material can be, for example, a polymer, an oxide layer, or a photoresist.

    摘要翻译: 提供了一种图像传感器及其制造方法。 可以在对应于每个单位像素的光接收装置的区域中通过图像传感器的金属互连层形成沟槽。 可以在沟槽的侧壁处提供钝化层图案,以抑制入射到金属互连层中的光并减少串扰和噪声。 可以提供填充材料以填充沟槽。 可以在填充材料上形成滤色器层和微透镜。 填充材料可以是例如聚合物,氧化物层或光致抗蚀剂。

    Semiconductor device and method of manufacturing the same
    5.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07482276B2

    公开(公告)日:2009-01-27

    申请号:US11613210

    申请日:2006-12-20

    IPC分类号: H01L21/311

    摘要: A semiconductor device and method of manufacturing same, capable of preventing the material of a barrier metal layer from penetrating into an intermetallic insulating layer are provided. In an embodiment, the device can include: a first metal interconnection formed in a lower insulating layer on a semiconductor substrate; an intermetallic insulating layer formed on the lower insulating layer including the first metal interconnection, the intermetallic insulating layer having a via hole and a trench for a second metal interconnection connecting to the first metal interconnection; a carbon implantation layer formed on inner walls of the via hole and the trench of the intermetallic insulating layer; a barrier metal layer deposited on the first metal interconnection exposed through the via hole and on the carbon implantation layer; a via formed in the via hole; and the second metal interconnection formed in the trench.

    摘要翻译: 提供了能够防止阻挡金属层的材料渗透到金属间绝缘层中的半导体器件及其制造方法。 在一个实施例中,该器件可以包括:形成在半导体衬底上的下绝缘层中的第一金属互连; 形成在包括第一金属互连的下绝缘层上的金属间绝缘层,具有通孔的金属间绝缘层和连接到第一金属互连的第二金属互连的沟槽; 在所述通孔的内壁和所述金属间绝缘层的沟槽上形成的碳注入层; 沉积在通过通孔和碳注入层暴露的第一金属互连上的阻挡金属层; 通孔形成在通孔中; 以及形成在沟槽中的第二金属互连。

    Method for manufacturing semiconductor device
    6.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US07427561B2

    公开(公告)日:2008-09-23

    申请号:US11293081

    申请日:2005-12-05

    申请人: Han Choon Lee

    发明人: Han Choon Lee

    IPC分类号: H01L21/00 H01L21/44

    摘要: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer; performing an annealing process upon the semiconductor substrate, to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer remained without reaction with the gate electrode and the semiconductor substrate.

    摘要翻译: 一种其中通过原位工艺形成金属硅化物层的半导体器件制造方法。 该方法包括在半导体衬底上形成栅电极; 在栅电极的任一侧面上形成绝缘侧壁; 在所述栅电极的任一侧在所述半导体衬底的表面中形成源/漏区; 在包括栅电极的半导体衬底的表面上形成金属层; 对金属层进行等离子体处理; 在所述金属层上形成覆盖材料层; 在半导体衬底上进行退火处理,在对应于栅电极和源极/漏极区的位置处在半导体衬底的表面上形成金属硅化物层; 并且除去覆盖材料层和金属层而不与栅电极和半导体衬底反应。

    Semiconductor device having a metal interconnection and method of fabricating the same
    7.
    发明申请
    Semiconductor device having a metal interconnection and method of fabricating the same 审中-公开
    具有金属互连的半导体器件及其制造方法

    公开(公告)号:US20080157375A1

    公开(公告)日:2008-07-03

    申请号:US11893009

    申请日:2007-08-13

    申请人: Han Choon Lee

    发明人: Han Choon Lee

    IPC分类号: H01L21/4763 H01L23/48

    摘要: Disclosed are a semiconductor device and a method for fabricating a metal interconnection of a semiconductor device. The method includes the steps of forming a dielectric layer on a semiconductor substrate including a lower interconnection, forming a trench in the interlayer dielectric layer that exposes the lower interconnection, forming a diffusion barrier in the trench and on the interlayer dielectric layer, forming a copper seed layer on the diffusion barrier, implanting a metal dopant into the copper seed layer, forming a copper metal interconnection on the copper seed layer into which the metal dopant is implanted, and forming an alloy layer from the copper seed layer and the metal dopant.

    摘要翻译: 公开了一种用于制造半导体器件的金属互连的半导体器件和方法。 该方法包括以下步骤:在包括下互连的半导体衬底上形成电介质层,在层间电介质层中形成沟槽,暴露下互连,在沟槽和层间绝缘层上形成扩散阻挡层,形成铜 种子层,在铜籽晶层上注入金属掺杂剂,在铜籽晶层上形成铜金属互连物,金属掺杂剂注入到该铜籽晶层中,从铜籽晶层和金属掺杂剂形成合金层。

    Semiconductor Device and Method of Manufacturing the Same
    8.
    发明申请
    Semiconductor Device and Method of Manufacturing the Same 失效
    半导体器件及其制造方法

    公开(公告)号:US20070152336A1

    公开(公告)日:2007-07-05

    申请号:US11613210

    申请日:2006-12-20

    IPC分类号: H01L23/52

    摘要: A semiconductor device and method of manufacturing same, capable of preventing the material of a barrier metal layer from penetrating into an intermetallic insulating layer are provided. In an embodiment, the device can include: a first metal interconnection formed in a lower insulating layer on a semiconductor substrate; an intermetallic insulating layer formed on the lower insulating layer including the first metal interconnection, the intermetallic insulating layer having a via hole and a trench for a second metal interconnection connecting to the first metal interconnection; a carbon implantation layer formed on inner walls of the via hole and the trench of the intermetallic insulating layer; a barrier metal layer deposited on the first metal interconnection exposed through the via hole and on the carbon implantation layer; a via formed in the via hole; and the second metal interconnection formed in the trench.

    摘要翻译: 提供了能够防止阻挡金属层的材料渗透到金属间绝缘层中的半导体器件及其制造方法。 在一个实施例中,该器件可以包括:形成在半导体衬底上的下绝缘层中的第一金属互连; 形成在包括第一金属互连的下绝缘层上的金属间绝缘层,具有通孔的金属间绝缘层和连接到第一金属互连的第二金属互连的沟槽; 在所述通孔的内壁和所述金属间绝缘层的沟槽上形成的碳注入层; 沉积在通过通孔和碳注入层暴露的第一金属互连上的阻挡金属层; 通孔形成在通孔中; 以及形成在沟槽中的第二金属互连。

    Semiconductor device and method of fabricating the same
    9.
    发明授权
    Semiconductor device and method of fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07880242B2

    公开(公告)日:2011-02-01

    申请号:US11876010

    申请日:2007-10-22

    申请人: Han Choon Lee

    发明人: Han Choon Lee

    IPC分类号: H01L29/78 H01L21/336

    摘要: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a gate insulating layer with a high dielectric constant (k) and a polysilicon layer on a gate metal layer. The gate metal layer can include silicon atoms. Electron mobility can be improved, and production residue and damage can be minimized.

    摘要翻译: 提供了一种半导体器件及其制造方法。 半导体器件包括具有高介电常数(k)的栅极绝缘层和栅极金属层上的多晶硅层。 栅极金属层可以包括硅原子。 可以改善电子迁移率,并且可以最小化生产残留和损伤。

    Metal Interconnection and Method for Manufacturing the Same in a Semiconductor Device
    10.
    发明申请
    Metal Interconnection and Method for Manufacturing the Same in a Semiconductor Device 审中-公开
    金属互连及其半导体器件制造方法

    公开(公告)号:US20090152735A1

    公开(公告)日:2009-06-18

    申请号:US12241212

    申请日:2008-09-30

    IPC分类号: H01L23/48 H01L21/4763

    CPC分类号: H01L21/28562 H01L21/76864

    摘要: Provided is a method for manufacturing a metal interconnection in a semiconductor device. The semiconductor device fabricated according to one embodiment comprises a copper interconnection having reduced sheet and contact resistance. In the method for manufacturing the copper interconnection, a dielectric comprising a via hole is formed on a semiconductor substrate. A diffusion barrier is deposited in the via hole of the dielectric using a process including a plasma enhanced atomic layer deposition (PEALD) process. A copper metal layer can be formed on the via hole through an electroplating process.

    摘要翻译: 提供一种在半导体器件中制造金属互连的方法。 根据一个实施例制造的半导体器件包括具有降低的片和接触电阻的铜互连。 在制造铜互连的方法中,在半导体衬底上形成包括通孔的电介质。 使用包括等离子体增强原子层沉积(PEALD)工艺的工艺在电介质的通孔中沉积扩散阻挡层。 可以通过电镀工艺在通孔上形成铜金属层。